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authorRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-05 10:36:45 +0000
committerRichard Sandiford <rsandifo@linux.vnet.ibm.com>2013-09-05 10:36:45 +0000
commit16277c4698f36a756c540fae326874774156aaed (patch)
tree640d07133c8f2ab9f909e7b2c464f96e6c1a5496 /lib/Target/SystemZ/SystemZInstrFP.td
parenta83aeae350d822ec84ded34ff3fdf1e0917d3bfd (diff)
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[SystemZ] Add NC, OC and XC
For now these are just used to handle scalar ANDs, ORs and XORs in which all operands are memory. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190041 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrFP.td')
-rw-r--r--lib/Target/SystemZ/SystemZInstrFP.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrFP.td b/lib/Target/SystemZ/SystemZInstrFP.td
index 8d0dcb6..24adaee 100644
--- a/lib/Target/SystemZ/SystemZInstrFP.td
+++ b/lib/Target/SystemZ/SystemZInstrFP.td
@@ -86,9 +86,9 @@ def : CopySign128<FP64, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
def : CopySign128<FP128, (CPSDRdd (EXTRACT_SUBREG FP128:$src1, subreg_high),
(EXTRACT_SUBREG FP128:$src2, subreg_high))>;
-defm LoadStoreF32 : MVCLoadStore<load, store, f32, MVCSequence, 4>;
-defm LoadStoreF64 : MVCLoadStore<load, store, f64, MVCSequence, 8>;
-defm LoadStoreF128 : MVCLoadStore<load, store, f128, MVCSequence, 16>;
+defm LoadStoreF32 : MVCLoadStore<load, f32, MVCSequence, 4>;
+defm LoadStoreF64 : MVCLoadStore<load, f64, MVCSequence, 8>;
+defm LoadStoreF128 : MVCLoadStore<load, f128, MVCSequence, 16>;
//===----------------------------------------------------------------------===//
// Load instructions