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author | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:41:52 +0000 |
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committer | Richard Sandiford <rsandifo@linux.vnet.ibm.com> | 2013-10-01 14:41:52 +0000 |
commit | bd1958d8e99ebd5a885f848b2f688c399cfc9886 (patch) | |
tree | b6e601bf608dbf79bf81ad61465325d83ac3bd18 /lib/Target/SystemZ/SystemZInstrInfo.td | |
parent | f985f01574956da0d42e33d440deb63bf153d354 (diff) | |
download | external_llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.zip external_llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.tar.gz external_llvm-bd1958d8e99ebd5a885f848b2f688c399cfc9886.tar.bz2 |
[SystemZ] Extend test-under-mask support to high GR32s
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@191773 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ/SystemZInstrInfo.td')
-rw-r--r-- | lib/Target/SystemZ/SystemZInstrInfo.td | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/lib/Target/SystemZ/SystemZInstrInfo.td b/lib/Target/SystemZ/SystemZInstrInfo.td index 88508e3..340580a 100644 --- a/lib/Target/SystemZ/SystemZInstrInfo.td +++ b/lib/Target/SystemZ/SystemZInstrInfo.td @@ -1140,16 +1140,22 @@ let mayLoad = 1, Defs = [CC], Uses = [R0L] in // Test under mask. let Defs = [CC] in { + // TMxMux expands to TM[LH]x, depending on the choice of register. + def TMLMux : CompareRIPseudo<z_tm_reg, GRX32, imm32ll16>, + Requires<[FeatureHighWord]>; + def TMHMux : CompareRIPseudo<z_tm_reg, GRX32, imm32lh16>, + Requires<[FeatureHighWord]>; def TMLL : CompareRI<"tmll", 0xA71, z_tm_reg, GR32, imm32ll16>; def TMLH : CompareRI<"tmlh", 0xA70, z_tm_reg, GR32, imm32lh16>; - - def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GR64, imm64hl16>; - def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GR64, imm64hh16>; + def TMHL : CompareRI<"tmhl", 0xA73, z_tm_reg, GRH32, imm32ll16>; + def TMHH : CompareRI<"tmhh", 0xA72, z_tm_reg, GRH32, imm32lh16>; defm TM : CompareSIPair<"tm", 0x91, 0xEB51, z_tm_mem, anyextloadi8, imm32zx8>; } -def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16>; -def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16>; +def : CompareGR64RI<TMLL, z_tm_reg, imm64ll16, subreg_l32>; +def : CompareGR64RI<TMLH, z_tm_reg, imm64lh16, subreg_l32>; +def : CompareGR64RI<TMHL, z_tm_reg, imm64hl16, subreg_h32>; +def : CompareGR64RI<TMHH, z_tm_reg, imm64hh16, subreg_h32>; //===----------------------------------------------------------------------===// // Prefetch |