Add a way to define the bit range covered by a SubRegIndex.

NOTE: If this broke your out-of-tree backend, in *RegisterInfo.td, change
the instances of SubRegIndex that have a comps template arg to use the
ComposedSubRegIndex class instead.

In TableGen land, this adds Size and Offset attributes to SubRegIndex,
and the ComposedSubRegIndex class, for which the Size and Offset are
computed by TableGen. This also adds an accessor in MCRegisterInfo, and
Size/Offsets for the X86 and ARM subreg indices.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183020 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 1 deletions

diff --git a/lib/Target/SystemZ/SystemZRegisterInfo.td b/lib/Target/SystemZ/SystemZRegisterInfo.td
index 7e4f0b9..7795fff 100644
--- a/lib/Target/SystemZ/SystemZRegisterInfo.td
+++ b/lib/Target/SystemZ/SystemZRegisterInfo.td
@@ -24,7 +24,7 @@ let Namespace = "SystemZ" in {
 def subreg_32bit  : SubRegIndex; // could also be known as "subreg_high32"
 def subreg_high   : SubRegIndex;
 def subreg_low    : SubRegIndex;
-def subreg_low32  : SubRegIndex<[subreg_low, subreg_32bit]>;
+def subreg_low32  : ComposedSubRegIndex<subreg_low, subreg_32bit>;
 }
 
 // Define a register class that contains values of type TYPE and an