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author | Chris Lattner <sabre@nondot.org> | 2010-09-21 20:31:19 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-09-21 20:31:19 +0000 |
commit | 52a261b3c1391c5fec399ddeb3fc6ee9541e8790 (patch) | |
tree | 800a9930728ffcc9d6f9a371dce4420ba7828c8c /lib/Target/SystemZ | |
parent | 7c727072168c55493ec362e254af1cd740d7eaf2 (diff) | |
download | external_llvm-52a261b3c1391c5fec399ddeb3fc6ee9541e8790.zip external_llvm-52a261b3c1391c5fec399ddeb3fc6ee9541e8790.tar.gz external_llvm-52a261b3c1391c5fec399ddeb3fc6ee9541e8790.tar.bz2 |
fix a long standing wart: all the ComplexPattern's were being
passed the root of the match, even though only a few patterns
actually needed this (one in X86, several in ARM [which should
be refactored anyway], and some in CellSPU that I don't feel
like detangling). Instead of requiring all ComplexPatterns to
take the dead root, have targets opt into getting the root by
putting SDNPWantRoot on the ComplexPattern.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@114471 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/SystemZ')
-rw-r--r-- | lib/Target/SystemZ/SystemZISelDAGToDAG.cpp | 29 |
1 files changed, 14 insertions, 15 deletions
diff --git a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp index a1eb6b3..2186ff1 100644 --- a/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp +++ b/lib/Target/SystemZ/SystemZISelDAGToDAG.cpp @@ -120,18 +120,17 @@ namespace { #include "SystemZGenDAGISel.inc" private: - bool SelectAddrRI12Only(SDNode *Op, SDValue& Addr, + bool SelectAddrRI12Only(SDValue& Addr, SDValue &Base, SDValue &Disp); - bool SelectAddrRI12(SDNode *Op, SDValue& Addr, + bool SelectAddrRI12(SDValue& Addr, SDValue &Base, SDValue &Disp, bool is12BitOnly = false); - bool SelectAddrRI(SDNode *Op, SDValue& Addr, - SDValue &Base, SDValue &Disp); - bool SelectAddrRRI12(SDNode *Op, SDValue Addr, + bool SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp); + bool SelectAddrRRI12(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); - bool SelectAddrRRI20(SDNode *Op, SDValue Addr, + bool SelectAddrRRI20(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); - bool SelectLAAddr(SDNode *Op, SDValue Addr, + bool SelectLAAddr(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index); SDNode *Select(SDNode *Node); @@ -353,12 +352,12 @@ void SystemZDAGToDAGISel::getAddressOperands(const SystemZRRIAddressMode &AM, /// Returns true if the address can be represented by a base register plus /// an unsigned 12-bit displacement [r+imm]. -bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI12Only(SDValue &Addr, SDValue &Base, SDValue &Disp) { - return SelectAddrRI12(Op, Addr, Base, Disp, /*is12BitOnly*/true); + return SelectAddrRI12(Addr, Base, Disp, /*is12BitOnly*/true); } -bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI12(SDValue &Addr, SDValue &Base, SDValue &Disp, bool is12BitOnly) { SystemZRRIAddressMode AM20(/*isRI*/true), AM12(/*isRI*/true); @@ -408,7 +407,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI12(SDNode *Op, SDValue& Addr, /// Returns true if the address can be represented by a base register plus /// a signed 20-bit displacement [r+imm]. -bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr, +bool SystemZDAGToDAGISel::SelectAddrRI(SDValue& Addr, SDValue &Base, SDValue &Disp) { SystemZRRIAddressMode AM(/*isRI*/true); bool Done = false; @@ -451,7 +450,7 @@ bool SystemZDAGToDAGISel::SelectAddrRI(SDNode *Op, SDValue& Addr, /// Returns true if the address can be represented by a base register plus /// index register plus an unsigned 12-bit displacement [base + idx + imm]. -bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectAddrRRI12(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM20, AM12; bool Done = false; @@ -500,7 +499,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI12(SDNode *Op, SDValue Addr, /// Returns true if the address can be represented by a base register plus /// index register plus a signed 20-bit displacement [base + idx + imm]. -bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectAddrRRI20(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM; bool Done = false; @@ -544,7 +543,7 @@ bool SystemZDAGToDAGISel::SelectAddrRRI20(SDNode *Op, SDValue Addr, /// SelectLAAddr - it calls SelectAddr and determines if the maximal addressing /// mode it matches can be cost effectively emitted as an LA/LAY instruction. -bool SystemZDAGToDAGISel::SelectLAAddr(SDNode *Op, SDValue Addr, +bool SystemZDAGToDAGISel::SelectLAAddr(SDValue Addr, SDValue &Base, SDValue &Disp, SDValue &Index) { SystemZRRIAddressMode AM; @@ -581,7 +580,7 @@ bool SystemZDAGToDAGISel::TryFoldLoad(SDNode *P, SDValue N, SDValue &Base, SDValue &Disp, SDValue &Index) { if (ISD::isNON_EXTLoad(N.getNode()) && IsLegalToFold(N, P, P, OptLevel)) - return SelectAddrRRI20(P, N.getOperand(1), Base, Disp, Index); + return SelectAddrRRI20(N.getOperand(1), Base, Disp, Index); return false; } |