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authorElena Demikhovsky <elena.demikhovsky@intel.com>2013-08-22 12:18:28 +0000
committerElena Demikhovsky <elena.demikhovsky@intel.com>2013-08-22 12:18:28 +0000
commit1765e74c15c83db437018a3c9efabbeb4ce9cbde (patch)
tree5bffe4d37b2c724573504c41789f04d8c4f420ea /lib/Target/X86/MCTargetDesc
parent7ddda4704cdb24163591857e8d08614463cec335 (diff)
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external_llvm-1765e74c15c83db437018a3c9efabbeb4ce9cbde.tar.gz
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AVX-512: Added masked SHIFT commands, more encoding tests
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@189005 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/MCTargetDesc')
-rw-r--r--lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp11
1 files changed, 6 insertions, 5 deletions
diff --git a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
index 7173d51..0c9fd91 100644
--- a/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
+++ b/lib/Target/X86/MCTargetDesc/X86MCCodeEmitter.cpp
@@ -868,11 +868,12 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte,
case X86II::MRM6r: case X86II::MRM7r:
// MRM0r-MRM7r instructions forms:
// dst(VEX_4V), src(ModR/M), imm8
- VEX_4V = getVEXRegisterEncoding(MI, CurOp);
- if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
- EVEX_V2 = 0x0;
- CurOp++;
-
+ if (HasVEX_4V) {
+ VEX_4V = getVEXRegisterEncoding(MI, CurOp);
+ if (HasEVEX && X86II::is32ExtendedReg(MI.getOperand(CurOp).getReg()))
+ EVEX_V2 = 0x0;
+ CurOp++;
+ }
if (HasEVEX_K)
EVEX_aaa = getWriteMaskRegisterEncoding(MI, CurOp++);