diff options
author | Chris Lattner <sabre@nondot.org> | 2010-03-04 19:48:19 +0000 |
---|---|---|
committer | Chris Lattner <sabre@nondot.org> | 2010-03-04 19:48:19 +0000 |
commit | 225d4ca8ab7c7d0e7fa0c7d43d95308b16edc554 (patch) | |
tree | b8ba72157f506ac87f257f96246f26be28f4b69a /lib/Target/X86/X86FastISel.cpp | |
parent | c19ae9d91d30bc008e0be5f5d4727f333199f64c (diff) | |
download | external_llvm-225d4ca8ab7c7d0e7fa0c7d43d95308b16edc554.zip external_llvm-225d4ca8ab7c7d0e7fa0c7d43d95308b16edc554.tar.gz external_llvm-225d4ca8ab7c7d0e7fa0c7d43d95308b16edc554.tar.bz2 |
make gep matching in fastisel match the base of the gep as a
register if it isn't possible to match the indexes *and* the base.
This fixes some fast isel rejects of load instructions on oggenc.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@97739 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86FastISel.cpp')
-rw-r--r-- | lib/Target/X86/X86FastISel.cpp | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp index 17366ee..c6da5cc 100644 --- a/lib/Target/X86/X86FastISel.cpp +++ b/lib/Target/X86/X86FastISel.cpp @@ -425,10 +425,17 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM) { break; // Ok, the GEP indices were covered by constant-offset and scaled-index // addressing. Update the address state and move on to examining the base. + X86AddressMode SavedAM = AM; AM.IndexReg = IndexReg; AM.Scale = Scale; AM.Disp = (uint32_t)Disp; - return X86SelectAddress(U->getOperand(0), AM); + if (X86SelectAddress(U->getOperand(0), AM)) + return true; + + // If we couldn't merge the sub value into this addr mode, revert back to + // our address and just match the value instead of completely failing. + AM = SavedAM; + break; unsupported_gep: // Ok, the GEP indices weren't all covered. break; |