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author | Rafael Espindola <rafael.espindola@gmail.com> | 2010-11-27 20:43:02 +0000 |
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committer | Rafael Espindola <rafael.espindola@gmail.com> | 2010-11-27 20:43:02 +0000 |
commit | 5bf7c534cf057a52f30624743841fadd241c4dbb (patch) | |
tree | cccf02d5385dd060adf6caa6a778ee52c3d930ea /lib/Target/X86/X86ISelLowering.cpp | |
parent | bfd2d26159c87262fcf462ea442f99478a2093c9 (diff) | |
download | external_llvm-5bf7c534cf057a52f30624743841fadd241c4dbb.zip external_llvm-5bf7c534cf057a52f30624743841fadd241c4dbb.tar.gz external_llvm-5bf7c534cf057a52f30624743841fadd241c4dbb.tar.bz2 |
Lower TLS_addr32 and TLS_addr64.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@120225 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 6793b70..91768d4 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -9923,6 +9923,44 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI, } MachineBasicBlock * +X86TargetLowering::emitLoweredTLSAddr(MachineInstr *MI, + MachineBasicBlock *BB) const { + const X86InstrInfo *TII + = static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo()); + DebugLoc DL = MI->getDebugLoc(); + if (Subtarget->is64Bit()) { + BuildMI(*BB, MI, DL, TII->get(X86::DATA16_PREFIX)); + MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(X86::LEA64r), + X86::RDI); + X86AddressMode Addr; + Addr.GV = MI->getOperand(3).getGlobal(); + Addr.GVOpFlags = MI->getOperand(3).getTargetFlags(); + Addr.Base.Reg = X86::RIP; + addFullAddress(MIB, Addr); + BuildMI(*BB, MI, DL, TII->get(X86::DATA16_PREFIX)); + BuildMI(*BB, MI, DL, TII->get(X86::DATA16_PREFIX)); + BuildMI(*BB, MI, DL, TII->get(X86::REX64_PREFIX)); + BuildMI(*BB, MI, DL, TII->get(X86::CALL64pcrel32)) + .addExternalSymbol("__tls_get_addr", X86II::MO_PLT) + .addReg(X86::RDI, RegState::Implicit); + } else { + MachineInstrBuilder MIB = BuildMI(*BB, MI, DL, TII->get(X86::LEA32r), + X86::EAX); + X86AddressMode Addr; + Addr.GV = MI->getOperand(3).getGlobal(); + Addr.GVOpFlags = MI->getOperand(3).getTargetFlags(); + Addr.IndexReg = X86::EBX; + addFullAddress(MIB, Addr); + BuildMI(*BB, MI, DL, TII->get(X86::CALLpcrel32)) + .addExternalSymbol("___tls_get_addr", X86II::MO_PLT) + .addReg(X86::EAX, RegState::Implicit); + } + + MI->eraseFromParent(); // The pseudo instruction is gone now. + return BB; +} + +MachineBasicBlock * X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *BB) const { switch (MI->getOpcode()) { @@ -9932,6 +9970,9 @@ X86TargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, case X86::TLSCall_32: case X86::TLSCall_64: return EmitLoweredTLSCall(MI, BB); + case X86::TLS_addr32: + case X86::TLS_addr64: + return emitLoweredTLSAddr(MI, BB); case X86::CMOV_GR8: case X86::CMOV_FR32: case X86::CMOV_FR64: |