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authorMon P Wang <wangmp@apple.com>2009-01-15 21:10:20 +0000
committerMon P Wang <wangmp@apple.com>2009-01-15 21:10:20 +0000
commitac2a3c58747bb0c9e9ca716b30c042bf0e2b38e2 (patch)
treeff1aac0fc589d099b58b5f7393817c1607aa6db3 /lib/Target/X86/X86ISelLowering.cpp
parenta168fc98dedfc8cac01c34f84b699fe5f48ad76d (diff)
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Expand insert/extract of a <4 x i32> with a variable index.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp12
1 files changed, 10 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 9499a9d..e39036f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -766,12 +766,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// information.
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
- setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
+ setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
- setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
+ setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
if (Subtarget->is64Bit()) {
@@ -4248,6 +4248,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
Op.getOperand(1));
return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
+ } else if (VT == MVT::i32) {
+ // ExtractPS works with constant index.
+ if (isa<ConstantSDNode>(Op.getOperand(1)))
+ return Op;
}
return SDValue();
}
@@ -4362,6 +4366,10 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
+ } else if (EVT == MVT::i32) {
+ // InsertPS works with constant index.
+ if (isa<ConstantSDNode>(N2))
+ return Op;
}
return SDValue();
}