diff options
author | Michael J. Spencer <bigcheesegs@gmail.com> | 2010-10-20 23:40:27 +0000 |
---|---|---|
committer | Michael J. Spencer <bigcheesegs@gmail.com> | 2010-10-20 23:40:27 +0000 |
commit | 6e56b18e575228a4f7318297155fe6ba2502a39b (patch) | |
tree | 7a4e73ef21b121ef06e95cb1c40b13ba549fa22c /lib/Target/X86/X86ISelLowering.h | |
parent | 01aabdac44af241a9a70c3d6ef8d5007e3e80ce1 (diff) | |
download | external_llvm-6e56b18e575228a4f7318297155fe6ba2502a39b.zip external_llvm-6e56b18e575228a4f7318297155fe6ba2502a39b.tar.gz external_llvm-6e56b18e575228a4f7318297155fe6ba2502a39b.tar.bz2 |
Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116972 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.h')
-rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 34c72c9..fbd0734 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -76,7 +76,7 @@ namespace llvm { /// CALL, - /// RDTSC_DAG - This operation implements the lowering for + /// RDTSC_DAG - This operation implements the lowering for /// readcyclecounter RDTSC_DAG, @@ -171,14 +171,14 @@ namespace llvm { // TLSADDR - Thread Local Storage. TLSADDR, - + // TLSCALL - Thread Local Storage. When calling to an OS provided // thunk at the address from an earlier relocation. TLSCALL, // EH_RETURN - Exception Handling helpers. EH_RETURN, - + /// TC_RETURN - Tail call return. /// operand #0 chain /// operand #1 callee (register or absolute) @@ -195,7 +195,7 @@ namespace llvm { // CMPPD, CMPPS - Vector double/float comparison. // CMPPD, CMPPS - Vector double/float comparison. CMPPD, CMPPS, - + // PCMP* - Vector integer comparisons. PCMPEQB, PCMPEQW, PCMPEQD, PCMPEQQ, PCMPGTB, PCMPGTW, PCMPGTD, PCMPGTQ, @@ -206,7 +206,7 @@ namespace llvm { // MUL_IMM - X86 specific multiply by immediate. MUL_IMM, - + // PTEST - Vector bitwise comparisons PTEST, @@ -256,8 +256,8 @@ namespace llvm { // MINGW_ALLOCA - MingW's __alloca call to do stack probing. MINGW_ALLOCA, - // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, - // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - + // ATOMADD64_DAG, ATOMSUB64_DAG, ATOMOR64_DAG, ATOMAND64_DAG, + // ATOMXOR64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG - // Atomic 64-bit binary operations. ATOMADD64_DAG = ISD::FIRST_TARGET_MEMORY_OPCODE, ATOMSUB64_DAG, @@ -266,23 +266,23 @@ namespace llvm { ATOMAND64_DAG, ATOMNAND64_DAG, ATOMSWAP64_DAG, - + // Memory barrier MEMBARRIER, MFENCE, SFENCE, LFENCE, - + // LCMPXCHG_DAG, LCMPXCHG8_DAG - Compare and swap. LCMPXCHG_DAG, LCMPXCHG8_DAG, // VZEXT_LOAD - Load, scalar_to_vector, and zero extend. VZEXT_LOAD, - + // FNSTCW16m - Store FP control world into i16 memory. FNSTCW16m, - + /// FP_TO_INT*_IN_MEM - This instruction implements FP_TO_SINT with the /// integer destination in memory and a FP reg source. This corresponds /// to the X86::FIST*m instructions and the rounding mode change stuff. It @@ -291,7 +291,7 @@ namespace llvm { FP_TO_INT16_IN_MEM, FP_TO_INT32_IN_MEM, FP_TO_INT64_IN_MEM, - + /// FILD, FILD_FLAG - This instruction implements SINT_TO_FP with the /// integer source in memory and FP reg result. This corresponds to the /// X86::FILD*m instructions. It has three inputs (token chain, address, @@ -299,13 +299,13 @@ namespace llvm { /// also produces a flag). FILD, FILD_FLAG, - + /// FLD - This instruction implements an extending load to FP stack slots. /// This corresponds to the X86::FLD32m / X86::FLD64m. It takes a chain /// operand, ptr to load from, and a ValueType node indicating the type /// to load to. FLD, - + /// FST - This instruction implements a truncating store to FP stack /// slots. This corresponds to the X86::FST32m / X86::FST64m. It takes a /// chain operand, value to store, address, and a ValueType to store it @@ -315,7 +315,7 @@ namespace llvm { /// VAARG_64 - This instruction grabs the address of the next argument /// from a va_list. (reads and modifies the va_list in memory) VAARG_64 - + // WARNING: Do not add anything in the end unless you want the node to // have memop! In fact, starting from ATOMADD64_DAG all opcodes will be // thought as target memory ops! @@ -432,14 +432,14 @@ namespace llvm { /// getPICBaseSymbol - Return the X86-32 PIC base. MCSymbol *getPICBaseSymbol(const MachineFunction *MF, MCContext &Ctx) const; - + virtual unsigned getJumpTableEncoding() const; virtual const MCExpr * LowerCustomJumpTableEntry(const MachineJumpTableInfo *MJTI, const MachineBasicBlock *MBB, unsigned uid, MCContext &Ctx) const; - + /// getPICJumpTableRelocaBase - Returns relocation base for the given PIC /// jumptable. virtual SDValue getPICJumpTableRelocBase(SDValue Table, @@ -447,7 +447,7 @@ namespace llvm { virtual const MCExpr * getPICJumpTableRelocBaseExpr(const MachineFunction *MF, unsigned JTI, MCContext &Ctx) const; - + /// getStackPtrReg - Return the stack pointer register we are using: either /// ESP or RSP. unsigned getStackPtrReg() const { return X86StackPtr; } @@ -491,7 +491,7 @@ namespace llvm { virtual void ReplaceNodeResults(SDNode *N, SmallVectorImpl<SDValue>&Results, SelectionDAG &DAG) const; - + virtual SDValue PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const; /// isTypeDesirableForOp - Return true if the target has native support for @@ -510,7 +510,7 @@ namespace llvm { EmitInstrWithCustomInserter(MachineInstr *MI, MachineBasicBlock *MBB) const; - + /// getTargetNodeName - This method returns the name of a target specific /// DAG node. virtual const char *getTargetNodeName(unsigned Opcode) const; @@ -518,12 +518,12 @@ namespace llvm { /// getSetCCResultType - Return the ISD::SETCC ValueType virtual MVT::SimpleValueType getSetCCResultType(EVT VT) const; - /// computeMaskedBitsForTargetNode - Determine which of the bits specified - /// in Mask are known to be either zero or one and return them in the + /// computeMaskedBitsForTargetNode - Determine which of the bits specified + /// in Mask are known to be either zero or one and return them in the /// KnownZero/KnownOne bitsets. virtual void computeMaskedBitsForTargetNode(const SDValue Op, const APInt &Mask, - APInt &KnownZero, + APInt &KnownZero, APInt &KnownOne, const SelectionDAG &DAG, unsigned Depth = 0) const; @@ -535,20 +535,20 @@ namespace llvm { virtual bool isGAPlusOffset(SDNode *N, const GlobalValue* &GA, int64_t &Offset) const; - + SDValue getReturnAddressFrameIndex(SelectionDAG &DAG) const; virtual bool ExpandInlineAsm(CallInst *CI) const; - + ConstraintType getConstraintType(const std::string &Constraint) const; - + /// Examine constraint string and operand type and determine a weight value, /// where: -1 = invalid match, and 0 = so-so match to 3 = good match. /// The operand object must already have been set up with the operand type. virtual int getSingleConstraintMatchWeight( AsmOperandInfo &info, const char *constraint) const; - - std::vector<unsigned> + + std::vector<unsigned> getRegClassForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; @@ -562,15 +562,15 @@ namespace llvm { char ConstraintLetter, std::vector<SDValue> &Ops, SelectionDAG &DAG) const; - + /// getRegForInlineAsmConstraint - Given a physical register constraint /// (e.g. {edx}), return the register number and the register class for the /// register. This should only be used for C_Register constraints. On /// error, this returns a register number of 0. - std::pair<unsigned, const TargetRegisterClass*> + std::pair<unsigned, const TargetRegisterClass*> getRegForInlineAsmConstraint(const std::string &Constraint, EVT VT) const; - + /// isLegalAddressingMode - Return true if the addressing mode represented /// by AM is legal for this target, for a load/store of the specified type. virtual bool isLegalAddressingMode(const AddrMode &AM, const Type *Ty)const; @@ -625,7 +625,7 @@ namespace llvm { // shrink long double fp constant since fldt is very slow. return !X86ScalarSSEf64 || VT == MVT::f80; } - + const X86Subtarget* getSubtarget() const { return Subtarget; } @@ -666,8 +666,8 @@ namespace llvm { /// X86StackPtr - X86 physical register used as stack ptr. unsigned X86StackPtr; - - /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 + + /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 /// floating point ops. /// When SSE is available, use it for f32 operations. /// When SSE2 is available, use it for f64 operations. @@ -849,7 +849,7 @@ namespace llvm { unsigned immOpcL, unsigned immOpcH, bool invSrc = false) const; - + /// Utility function to emit atomic min and max. It takes the min/max /// instruction to expand, the associated basic block, and the associated /// cmov opcode for moving the min or max value. @@ -872,7 +872,7 @@ namespace llvm { MachineBasicBlock *EmitLoweredMingwAlloca(MachineInstr *MI, MachineBasicBlock *BB) const; - + MachineBasicBlock *EmitLoweredTLSCall(MachineInstr *MI, MachineBasicBlock *BB) const; |