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| author | Lang Hames <lhames@gmail.com> | 2013-10-21 17:51:24 +0000 |
|---|---|---|
| committer | Lang Hames <lhames@gmail.com> | 2013-10-21 17:51:24 +0000 |
| commit | 1d82537762a0f4019bde301d498d190140585f57 (patch) | |
| tree | 85024ec02b3891da0b68ca933c8b5a251534c394 /lib/Target/X86/X86InstrAVX512.td | |
| parent | ef2d919f7f767b9d70bc44c4ac918b0a6b540cac (diff) | |
| download | external_llvm-1d82537762a0f4019bde301d498d190140585f57.zip external_llvm-1d82537762a0f4019bde301d498d190140585f57.tar.gz external_llvm-1d82537762a0f4019bde301d498d190140585f57.tar.bz2 | |
X86 vector element shift-by-immediate instructions take i8 immediates. Make
the instruction defenitions and ISEL reflect this.
Prior to this patch these instructions took an i32i8imm, and the high bits were
dropped during encoding. This led to incorrect behavior for shifts by
immediates higher than 255. This patch fixes that issue by detecting large
immediate shifts and returning constant zero (for logical shifts) or capping
the shift amount at an encodable value (for arithmetic shifts).
Fixes <rdar://problem/14968098>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193096 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrAVX512.td')
| -rw-r--r-- | lib/Target/X86/X86InstrAVX512.td | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/lib/Target/X86/X86InstrAVX512.td b/lib/Target/X86/X86InstrAVX512.td index 3fd725c..05e346d 100644 --- a/lib/Target/X86/X86InstrAVX512.td +++ b/lib/Target/X86/X86InstrAVX512.td @@ -1845,22 +1845,22 @@ multiclass avx512_shift_rmi<bits<8> opc, Format ImmFormR, Format ImmFormM, ValueType vt, X86MemOperand x86memop, PatFrag mem_frag, RegisterClass KRC> { def ri : AVX512BIi8<opc, ImmFormR, (outs RC:$dst), - (ins RC:$src1, i32i8imm:$src2), + (ins RC:$src1, i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), - [(set RC:$dst, (vt (OpNode RC:$src1, (i32 imm:$src2))))], + [(set RC:$dst, (vt (OpNode RC:$src1, (i8 imm:$src2))))], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V; def rik : AVX512BIi8<opc, ImmFormR, (outs RC:$dst), - (ins KRC:$mask, RC:$src1, i32i8imm:$src2), + (ins KRC:$mask, RC:$src1, i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), [], SSE_INTSHIFT_ITINS_P.rr>, EVEX_4V, EVEX_K; def mi: AVX512BIi8<opc, ImmFormM, (outs RC:$dst), - (ins x86memop:$src1, i32i8imm:$src2), + (ins x86memop:$src1, i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), [(set RC:$dst, (OpNode (mem_frag addr:$src1), - (i32 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; + (i8 imm:$src2)))], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V; def mik: AVX512BIi8<opc, ImmFormM, (outs RC:$dst), - (ins KRC:$mask, x86memop:$src1, i32i8imm:$src2), + (ins KRC:$mask, x86memop:$src1, i8imm:$src2), !strconcat(OpcodeStr, "\t{$src2, $src1, $dst {${mask}}|$dst {${mask}}, $src1, $src2}"), [], SSE_INTSHIFT_ITINS_P.rm>, EVEX_4V, EVEX_K; |