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author | Chris Lattner <sabre@nondot.org> | 2010-10-05 21:18:04 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-10-05 21:18:04 +0000 |
commit | 2c383d8c4db7c3943396543b577707f56bf61772 (patch) | |
tree | 538eeedd55c1b0f8387dbbb81070190a8b3f2e92 /lib/Target/X86/X86InstrCompiler.td | |
parent | 508fc4708bb859391af8969614e67c84ab56c38c (diff) | |
download | external_llvm-2c383d8c4db7c3943396543b577707f56bf61772.zip external_llvm-2c383d8c4db7c3943396543b577707f56bf61772.tar.gz external_llvm-2c383d8c4db7c3943396543b577707f56bf61772.tar.bz2 |
move SETB pseudos into the same place in InstrCompiler.td
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@115686 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrCompiler.td')
-rw-r--r-- | lib/Target/X86/X86InstrCompiler.td | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index db6e5a4..9af6218 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -158,15 +158,24 @@ def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), "", [(set GR64:$dst, i64immZExt32:$src)]>; -// Use sbb to materialize carry flag into a GPR. -// FIXME: This are pseudo ops that should be replaced with Pat<> patterns. +// Use sbb to materialize carry bit. +let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in { +// FIXME: These are pseudo ops that should be replaced with Pat<> patterns. // However, Pat<> can't replicate the destination reg into the inputs of the // result. -// FIXME: Change this to have encoding Pseudo when X86MCCodeEmitter replaces +// FIXME: Change these to have encoding Pseudo when X86MCCodeEmitter replaces // X86CodeEmitter. -let Defs = [EFLAGS], Uses = [EFLAGS], isCodeGenOnly = 1 in +def SETB_C8r : I<0x18, MRMInitReg, (outs GR8:$dst), (ins), "", + [(set GR8:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +def SETB_C16r : I<0x19, MRMInitReg, (outs GR16:$dst), (ins), "", + [(set GR16:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>, + OpSize; +def SETB_C32r : I<0x19, MRMInitReg, (outs GR32:$dst), (ins), "", + [(set GR32:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; def SETB_C64r : RI<0x19, MRMInitReg, (outs GR64:$dst), (ins), "", [(set GR64:$dst, (X86setcc_c X86_COND_B, EFLAGS))]>; +} // isCodeGenOnly + def : Pat<(i64 (anyext (i8 (X86setcc_c X86_COND_B, EFLAGS)))), (SETB_C64r)>; |