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author | Chris Lattner <sabre@nondot.org> | 2010-10-31 19:15:18 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2010-10-31 19:15:18 +0000 |
commit | a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6 (patch) | |
tree | e35b8f463d5a99dbce85e6fa5bfd20382e89abbc /lib/Target/X86/X86InstrCompiler.td | |
parent | 39ee036f407bd0c94cb993cf9b97348843cfafa4 (diff) | |
download | external_llvm-a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6.zip external_llvm-a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6.tar.gz external_llvm-a4a3a5e3c212e7b4ac84fec94c9a140f120f3ff6.tar.bz2 |
two changes: make the asmmatcher generator ignore ARM pseudos properly,
and make it a hard error for instructions to not have an asm string.
These instructions should be marked isCodeGenOnly.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@117861 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrCompiler.td')
-rw-r--r-- | lib/Target/X86/X86InstrCompiler.td | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrCompiler.td b/lib/Target/X86/X86InstrCompiler.td index 64a7354..a9720b1 100644 --- a/lib/Target/X86/X86InstrCompiler.td +++ b/lib/Target/X86/X86InstrCompiler.td @@ -161,7 +161,7 @@ def MOV32r0 : I<0x31, MRMInitReg, (outs GR32:$dst), (ins), "", // instruction is lowered to an MCInst. // FIXME: AddedComplexity gives this a higher priority than MOV64ri32. Remove // when we have a better way to specify isel priority. -let Defs = [EFLAGS], +let Defs = [EFLAGS], isCodeGenOnly=1, AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", [(set GR64:$dst, 0)]>; @@ -169,11 +169,11 @@ def MOV64r0 : I<0x31, MRMInitReg, (outs GR64:$dst), (ins), "", // Materialize i64 constant where top 32-bits are zero. This could theoretically // use MOV32ri with a SUBREG_TO_REG to represent the zero-extension, however // that would make it more difficult to rematerialize. -let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1 in +let AddedComplexity = 1, isReMaterializable = 1, isAsCheapAsAMove = 1, + isCodeGenOnly = 1 in def MOV64ri64i32 : Ii32<0xB8, AddRegFrm, (outs GR64:$dst), (ins i64i32imm:$src), "", [(set GR64:$dst, i64immZExt32:$src)]>; - // Use sbb to materialize carry bit. let Uses = [EFLAGS], Defs = [EFLAGS], isCodeGenOnly = 1 in { // FIXME: These are pseudo ops that should be replaced with Pat<> patterns. |