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| author | Craig Topper <craig.topper@gmail.com> | 2012-07-30 06:48:11 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2012-07-30 06:48:11 +0000 |
| commit | 49d86c9eb95bf0233cf749c79f0e10d03f33c58e (patch) | |
| tree | 2648f6d6fa228972b7c5fa2f151e4e37a0b1464e /lib/Target/X86/X86InstrExtension.td | |
| parent | 95c929f45c01054d91a6878de22892675dd115cf (diff) | |
| download | external_llvm-49d86c9eb95bf0233cf749c79f0e10d03f33c58e.zip external_llvm-49d86c9eb95bf0233cf749c79f0e10d03f33c58e.tar.gz external_llvm-49d86c9eb95bf0233cf749c79f0e10d03f33c58e.tar.bz2 | |
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrExtension.td')
| -rw-r--r-- | lib/Target/X86/X86InstrExtension.td | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td index 0d5490a..7766671 100644 --- a/lib/Target/X86/X86InstrExtension.td +++ b/lib/Target/X86/X86InstrExtension.td @@ -82,6 +82,7 @@ def MOVZX32rm16: I<0xB7, MRMSrcMem, (outs GR32:$dst), (ins i16mem:$src), // These are the same as the regular MOVZX32rr8 and MOVZX32rm8 // except that they use GR32_NOREX for the output operand register class // instead of GR32. This allows them to operate on h registers on x86-64. +let neverHasSideEffects = 1, isCodeGenOnly = 1 in { def MOVZX32_NOREXrr8 : I<0xB6, MRMSrcReg, (outs GR32_NOREX:$dst), (ins GR8_NOREX:$src), "movz{bl|x}\t{$src, $dst|$dst, $src}", @@ -91,6 +92,7 @@ def MOVZX32_NOREXrm8 : I<0xB6, MRMSrcMem, (outs GR32_NOREX:$dst), (ins i8mem_NOREX:$src), "movz{bl|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, TB; +} // MOVSX64rr8 always has a REX prefix and it has an 8-bit register // operand, which makes it a rare instruction with an 8-bit register |