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| author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-26 18:24:22 +0000 |
|---|---|---|
| committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2013-03-26 18:24:22 +0000 |
| commit | b4f60e9f772de7152a0880d84c5ef511f6d2c642 (patch) | |
| tree | 864af03e20e9cace9efe503076bf7b389376b650 /lib/Target/X86/X86InstrExtension.td | |
| parent | 75f6310dc9977636b7416178153f23f3bbdba721 (diff) | |
| download | external_llvm-b4f60e9f772de7152a0880d84c5ef511f6d2c642.zip external_llvm-b4f60e9f772de7152a0880d84c5ef511f6d2c642.tar.gz external_llvm-b4f60e9f772de7152a0880d84c5ef511f6d2c642.tar.bz2 | |
Annotate the remaining x86 instructions with SchedRW lists.
Now all x86 instructions that have itinerary classes also have SchedRW
lists. This is required before the new scheduling models can be used.
There are still unannotated instructions remaining, but they don't have
itinerary classes either.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178051 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrExtension.td')
| -rw-r--r-- | lib/Target/X86/X86InstrExtension.td | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrExtension.td b/lib/Target/X86/X86InstrExtension.td index 5ef0c3c..6dc7175 100644 --- a/lib/Target/X86/X86InstrExtension.td +++ b/lib/Target/X86/X86InstrExtension.td @@ -138,16 +138,16 @@ def MOVSX64rm32: RI<0x63, MRMSrcMem, (outs GR64:$dst), (ins i32mem:$src), // movzbq and movzwq encodings for the disassembler def MOVZX64rr8_Q : RI<0xB6, MRMSrcReg, (outs GR64:$dst), (ins GR8:$src), "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, - TB; + TB, Sched<[WriteALU]>; def MOVZX64rm8_Q : RI<0xB6, MRMSrcMem, (outs GR64:$dst), (ins i8mem:$src), "movz{bq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, - TB; + TB, Sched<[WriteALULd]>; def MOVZX64rr16_Q : RI<0xB7, MRMSrcReg, (outs GR64:$dst), (ins GR16:$src), "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, - TB; + TB, Sched<[WriteALU]>; def MOVZX64rm16_Q : RI<0xB7, MRMSrcMem, (outs GR64:$dst), (ins i16mem:$src), "movz{wq|x}\t{$src, $dst|$dst, $src}", [], IIC_MOVZX>, - TB; + TB, Sched<[WriteALULd]>; // FIXME: These should be Pat patterns. let isCodeGenOnly = 1 in { |