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authorJan Sjödin <jan_sjodin@yahoo.com>2011-12-08 14:43:19 +0000
committerJan Sjödin <jan_sjodin@yahoo.com>2011-12-08 14:43:19 +0000
commit703420f50e458e2482e55c9a5b3cafa0b734f507 (patch)
treebcf6416bc486f71a94283afb990b31767ddee2ba /lib/Target/X86/X86InstrFMA.td
parent44bac7cd659090f15face5171e3c346983aeb521 (diff)
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Src2 and src3 were accidentally swapped for the FMA4 rr patterns. Undo this and fix the encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@146151 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrFMA.td')
-rw-r--r--lib/Target/X86/X86InstrFMA.td6
1 files changed, 3 insertions, 3 deletions
diff --git a/lib/Target/X86/X86InstrFMA.td b/lib/Target/X86/X86InstrFMA.td
index 015b01e..f443088 100644
--- a/lib/Target/X86/X86InstrFMA.td
+++ b/lib/Target/X86/X86InstrFMA.td
@@ -68,7 +68,7 @@ multiclass fma4s<bits<8> opc, string OpcodeStr> {
def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
- "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_W;
def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
@@ -87,7 +87,7 @@ multiclass fma4p<bits<8> opc, string OpcodeStr> {
def rr : FMA4<opc, MRMSrcReg, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, VR128:$src3),
!strconcat(OpcodeStr,
- "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_W;
def rm : FMA4<opc, MRMSrcMem, (outs VR128:$dst),
(ins VR128:$src1, VR128:$src2, f128mem:$src3),
@@ -102,7 +102,7 @@ multiclass fma4p<bits<8> opc, string OpcodeStr> {
def rrY : FMA4<opc, MRMSrcReg, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, VR256:$src3),
!strconcat(OpcodeStr,
- "\t{$src2, $src3, $src1, $dst|$dst, $src1, $src3, $src2}"),
+ "\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}"),
[]>, XOP_W;
def rmY : FMA4<opc, MRMSrcMem, (outs VR256:$dst),
(ins VR256:$src1, VR256:$src2, f256mem:$src3),