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authorPreston Gurd <preston.gurd@intel.com>2013-09-13 19:23:28 +0000
committerPreston Gurd <preston.gurd@intel.com>2013-09-13 19:23:28 +0000
commit94dc6540a8f3aaadb43dda50e49fc79141fae8ed (patch)
tree909ea42f4259ad0a03ffd2add982988f3c0185be /lib/Target/X86/X86InstrFormats.td
parent0df68423f9567b3d3eafb3b26668f783b07f687f (diff)
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Adds support for Atom Silvermont (SLM) - -march=slm
Implements Instruction scheduler latencies for Silvermont, using latencies from the Intel Silvermont Optimization Guide. Auto detects SLM. Turns on post RA scheduler when generating code for SLM. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190717 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrFormats.td')
-rw-r--r--lib/Target/X86/X86InstrFormats.td2
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrFormats.td b/lib/Target/X86/X86InstrFormats.td
index b50706c..fb07ed0 100644
--- a/lib/Target/X86/X86InstrFormats.td
+++ b/lib/Target/X86/X86InstrFormats.td
@@ -671,7 +671,7 @@ class AVX512FMA3<bits<8> o, Format F, dag outs, dag ins, string asm,
// AES8I
// These use the same encoding as the SSE4.2 T8 and TA encodings.
class AES8I<bits<8> o, Format F, dag outs, dag ins, string asm,
- list<dag>pattern, InstrItinClass itin = NoItinerary>
+ list<dag>pattern, InstrItinClass itin = IIC_AES>
: I<o, F, outs, ins, asm, pattern, itin, SSEPackedInt>, T8,
Requires<[HasAES]>;