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author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-05 03:53:24 +0000 |
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committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-06-05 03:53:24 +0000 |
commit | 3eca98bb3ab1ec27ab8763298c416d282cdaa261 (patch) | |
tree | d005476218b8d61b1d6fd2eb0ee2d93f522553b6 /lib/Target/X86/X86InstrInfo.h | |
parent | 270562b3d4c61ae1381cb1b0026bb703b46ff88f (diff) | |
download | external_llvm-3eca98bb3ab1ec27ab8763298c416d282cdaa261.zip external_llvm-3eca98bb3ab1ec27ab8763298c416d282cdaa261.tar.gz external_llvm-3eca98bb3ab1ec27ab8763298c416d282cdaa261.tar.bz2 |
Initial AVX support for some instructions. No patterns matched
yet, only assembly encoding support.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@105521 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.h')
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 22 |
1 files changed, 18 insertions, 4 deletions
diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index f5c8022..9016c16 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -417,22 +417,36 @@ namespace X86II { OpcodeShift = 24, OpcodeMask = 0xFF << OpcodeShift + }; + // FIXME: The enum opcode space is over and more bits are needed. Anywhere + // those enums below are used, TSFlags must be shifted right by 32 first. + enum { + //===------------------------------------------------------------------===// + // VEX_4V - VEX prefixes are instruction prefixes used in AVX. + // VEX_4V is used to specify an additional AVX/SSE register. Several 2 + // address instructions in SSE are represented as 3 address ones in AVX + // and the additional register is encoded in VEX_VVVV prefix. + // + VEXShift = 0, + VEX_4V = 1 << VEXShift + }; + // getBaseOpcodeFor - This function returns the "base" X86 opcode for the // specified machine instruction. // - static inline unsigned char getBaseOpcodeFor(unsigned TSFlags) { + static inline unsigned char getBaseOpcodeFor(uint64_t TSFlags) { return TSFlags >> X86II::OpcodeShift; } - static inline bool hasImm(unsigned TSFlags) { + static inline bool hasImm(uint64_t TSFlags) { return (TSFlags & X86II::ImmMask) != 0; } /// getSizeOfImm - Decode the "size of immediate" field from the TSFlags field /// of the specified instruction. - static inline unsigned getSizeOfImm(unsigned TSFlags) { + static inline unsigned getSizeOfImm(uint64_t TSFlags) { switch (TSFlags & X86II::ImmMask) { default: assert(0 && "Unknown immediate size"); case X86II::Imm8: @@ -446,7 +460,7 @@ namespace X86II { /// isImmPCRel - Return true if the immediate of the specified instruction's /// TSFlags indicates that it is pc relative. - static inline unsigned isImmPCRel(unsigned TSFlags) { + static inline unsigned isImmPCRel(uint64_t TSFlags) { switch (TSFlags & X86II::ImmMask) { default: assert(0 && "Unknown immediate size"); case X86II::Imm8PCRel: |