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author | Chris Lattner <sabre@nondot.org> | 2004-08-11 02:25:00 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2004-08-11 02:25:00 +0000 |
commit | 66fa1dcf9024fcb953a574394b0b7dd6320f6fe3 (patch) | |
tree | c04243dff0bbcac6558993321d53696cb425c64d /lib/Target/X86/X86InstrInfo.td | |
parent | 1caef2c0a9df447d6bdcba329675e52c51f3642b (diff) | |
download | external_llvm-66fa1dcf9024fcb953a574394b0b7dd6320f6fe3.zip external_llvm-66fa1dcf9024fcb953a574394b0b7dd6320f6fe3.tar.gz external_llvm-66fa1dcf9024fcb953a574394b0b7dd6320f6fe3.tar.bz2 |
Convert asmprinter to new style of instruction printer
Start asmprintergen'ifying machine instrs with memory operands.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@15646 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrInfo.td')
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 41 |
1 files changed, 33 insertions, 8 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 277ef28..9949791 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -13,6 +13,24 @@ // //===----------------------------------------------------------------------===// +// *mem - Operand definitions for the funky X86 addressing mode operands. +// +def i8mem : Operand<i8> { + let NumMIOperands = 4; + let PrintMethod = "printMemoryOperand"; +} + +def i16mem : Operand<i16> { + let NumMIOperands = 4; + let PrintMethod = "printMemoryOperand"; +} + +def i32mem : Operand<i32> { + let NumMIOperands = 4; + let PrintMethod = "printMemoryOperand"; +} + + // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. @@ -219,7 +237,8 @@ def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 (ops R32:$src1, R32:$src2), "xchg $src1, $src2">; -def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8 +def XCHG8mr : Im8 <"", 0x86, MRMDestMem>, // xchg [mem8], R8 + II<(ops i8mem:$src1, R8:$src2), "xchg $src1, $src2">; def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16 def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32 def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8] @@ -289,13 +308,19 @@ def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16 def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32 -def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8] -def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize; // R16 = [mem16] -def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>; // R32 = [mem32] - -def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8 -def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16 -def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32 +def MOV8rm : Im8 <"", 0x8A, MRMSrcMem>, // R8 = [mem8] + II<(ops R8 :$dst, i8mem :$src), "mov $dst, $src">; +def MOV16rm : Im16<"", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16] + II<(ops R16:$dst, i16mem:$src), "mov $dst, $src">; +def MOV32rm : Im32<"", 0x8B, MRMSrcMem>, // R32 = [mem32] + II<(ops R32:$dst, i32mem:$src), "mov $dst, $src">; + +def MOV8mr : Im8 <"", 0x88, MRMDestMem>, // [mem8] = R8 + II<(ops i8mem :$dst, R8 :$src), "mov $dst, $src">; +def MOV16mr : Im16<"", 0x89, MRMDestMem>, OpSize, // [mem16] = R16 + II<(ops i16mem:$dst, R16:$src), "mov $dst, $src">; +def MOV32mr : Im32<"", 0x89, MRMDestMem>, // [mem32] = R32 + II<(ops i32mem:$dst, R32:$src), "mov $dst, $src">; //===----------------------------------------------------------------------===// // Fixed-Register Multiplication and Division Instructions... |