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| author | Craig Topper <craig.topper@gmail.com> | 2013-10-14 01:42:32 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-10-14 01:42:32 +0000 |
| commit | 8e121843c19297205fe9acb9153570f596838eb9 (patch) | |
| tree | 0853174a297d18a94cf35753dedfe4b9bf96bfd2 /lib/Target/X86/X86InstrSSE.td | |
| parent | bae9f69d37a60aad0185cdf17434ec188c976e67 (diff) | |
| download | external_llvm-8e121843c19297205fe9acb9153570f596838eb9.zip external_llvm-8e121843c19297205fe9acb9153570f596838eb9.tar.gz external_llvm-8e121843c19297205fe9acb9153570f596838eb9.tar.bz2 | |
Add disassembler support for SSE4.1 register/register form of PEXTRW. There is a shorter encoding that was part of SSE2, but a memory form was added in SSE4.1. This is the register form of that encoding.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192566 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 90bdfa3..15b9b91 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -6053,6 +6053,13 @@ defm PEXTRB : SS41I_extract8<0x14, "pextrb">; /// SS41I_extract16 - SSE 4.1 extract 16 bits to memory destination multiclass SS41I_extract16<bits<8> opc, string OpcodeStr> { + let isCodeGenOnly = 1, hasSideEffects = 0 in + def rr_REV : SS4AIi8<opc, MRMDestReg, (outs GR32:$dst), + (ins VR128:$src1, i32i8imm:$src2), + !strconcat(OpcodeStr, + "\t{$src2, $src1, $dst|$dst, $src1, $src2}"), + []>, OpSize; + let neverHasSideEffects = 1, mayStore = 1 in def mr : SS4AIi8<opc, MRMDestMem, (outs), (ins i16mem:$dst, VR128:$src1, i32i8imm:$src2), |