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| author | Craig Topper <craig.topper@gmail.com> | 2013-10-07 05:42:48 +0000 |
|---|---|---|
| committer | Craig Topper <craig.topper@gmail.com> | 2013-10-07 05:42:48 +0000 |
| commit | 8fdba75d5b865246455c335adf439def1c3daaeb (patch) | |
| tree | 10367cba7f90d1814f80a8513b9bc04724166e27 /lib/Target/X86/X86InstrSSE.td | |
| parent | 36a9b31b981553350f5cc4adad9917656c20e96e (diff) | |
| download | external_llvm-8fdba75d5b865246455c335adf439def1c3daaeb.zip external_llvm-8fdba75d5b865246455c335adf439def1c3daaeb.tar.gz external_llvm-8fdba75d5b865246455c335adf439def1c3daaeb.tar.bz2 | |
Teach X86 asm parser that VMOVAPSrr and other VEX-encoded register to register moves should be switched from using the MRMSrcReg form to the MRMDestReg form if the source register is a 64-bit extended register and the destination register is not.
This allows the instruction to be encoded using the 2-byte VEX form instead of the 3-byte VEX form. The GNU assembler has similar behavior and instruction selection already does this.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192088 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 3d86549..f6f2266 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -1104,7 +1104,7 @@ let Predicates = [UseSSE1] in { // Alias instruction to do FR32 or FR64 reg-to-reg copy using movaps. Upper // bits are disregarded. FIXME: Set encoding to pseudo! -let neverHasSideEffects = 1, SchedRW = [WriteMove] in { +let isCodeGenOnly = 1, neverHasSideEffects = 1, SchedRW = [WriteMove] in { def FsVMOVAPSrr : VPSI<0x28, MRMSrcReg, (outs FR32:$dst), (ins FR32:$src), "movaps\t{$src, $dst|$dst, $src}", [], IIC_SSE_MOVA_P_RR>, VEX; |