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| author | Dan Gohman <gohman@apple.com> | 2009-07-30 01:56:29 +0000 |
|---|---|---|
| committer | Dan Gohman <gohman@apple.com> | 2009-07-30 01:56:29 +0000 |
| commit | a4714e025de720d0fcbaa78ab6c12dc789599233 (patch) | |
| tree | 5e129202d37b2e5937fff8d088a69f5691a749c0 /lib/Target/X86/X86InstrSSE.td | |
| parent | 2395f011986e6c6277c71bddcd8af88f9b904fc2 (diff) | |
| download | external_llvm-a4714e025de720d0fcbaa78ab6c12dc789599233.zip external_llvm-a4714e025de720d0fcbaa78ab6c12dc789599233.tar.gz external_llvm-a4714e025de720d0fcbaa78ab6c12dc789599233.tar.bz2 | |
Add a new register class to describe operands that can't be SP,
due to x86 encoding restrictions. This is currently off by default
because it may cause code quality regressions. This is for PR4572.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77565 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 853f88e..2440aec 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -86,11 +86,11 @@ def sse_load_f64 : ComplexPattern<v2f64, 5, "SelectScalarSSELoad", [], def ssmem : Operand<v4f32> { let PrintMethod = "printf32mem"; - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm); + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); } def sdmem : Operand<v2f64> { let PrintMethod = "printf64mem"; - let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc, i32imm, i8imm); + let MIOperandInfo = (ops ptr_rc, i8imm, ptr_rc_nosp, i32imm, i8imm); } //===----------------------------------------------------------------------===// |