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| author | Evan Cheng <evan.cheng@apple.com> | 2009-12-22 17:47:23 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2009-12-22 17:47:23 +0000 |
| commit | b1f49813334278094b1ecd7ad920f5c276f7b3e6 (patch) | |
| tree | 0870255a6e4a8ec474c2762244d59666b63ba755 /lib/Target/X86/X86InstrSSE.td | |
| parent | 3dac3b7d2369bc7d051d0f709d63c321c1375532 (diff) | |
| download | external_llvm-b1f49813334278094b1ecd7ad920f5c276f7b3e6.zip external_llvm-b1f49813334278094b1ecd7ad920f5c276f7b3e6.tar.gz external_llvm-b1f49813334278094b1ecd7ad920f5c276f7b3e6.tar.bz2 | |
Remove target attribute break-sse-dep. Instead, do not fold load into sse partial update instructions unless optimizing for size.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91910 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 694b91e..b26e508 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -827,7 +827,7 @@ multiclass sse1_fp_unop_rm<bits<8> opc, string OpcodeStr, def SSm : I<opc, MRMSrcMem, (outs FR32:$dst), (ins f32mem:$src), !strconcat(OpcodeStr, "ss\t{$src, $dst|$dst, $src}"), [(set FR32:$dst, (OpNode (load addr:$src)))]>, XS, - Requires<[HasSSE1, NoSSEBreakDep]>; + Requires<[HasSSE1, OptForSize]>; // Vector operation, reg. def PSr : PSI<opc, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), @@ -1120,7 +1120,7 @@ def CVTSD2SSrr : SDI<0x5A, MRMSrcReg, (outs FR32:$dst), (ins FR64:$src), def CVTSD2SSrm : I<0x5A, MRMSrcMem, (outs FR32:$dst), (ins f64mem:$src), "cvtsd2ss\t{$src, $dst|$dst, $src}", [(set FR32:$dst, (fround (loadf64 addr:$src)))]>, XD, - Requires<[HasSSE2, NoSSEBreakDep]>; + Requires<[HasSSE2, OptForSize]>; def CVTSI2SDrr : SDI<0x2A, MRMSrcReg, (outs FR64:$dst), (ins GR32:$src), "cvtsi2sd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (sint_to_fp GR32:$src))]>; @@ -1157,10 +1157,10 @@ def CVTSS2SDrr : I<0x5A, MRMSrcReg, (outs FR64:$dst), (ins FR32:$src), def CVTSS2SDrm : I<0x5A, MRMSrcMem, (outs FR64:$dst), (ins f32mem:$src), "cvtss2sd\t{$src, $dst|$dst, $src}", [(set FR64:$dst, (extloadf32 addr:$src))]>, XS, - Requires<[HasSSE2, NoSSEBreakDep]>; + Requires<[HasSSE2, OptForSize]>; def : Pat<(extloadf32 addr:$src), - (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[SSEBreakDep]>; + (CVTSS2SDrr (MOVSSrm addr:$src))>, Requires<[HasSSE2, OptForSpeed]>; // Match intrinsics which expect XMM operand(s). def Int_CVTSD2SIrr : SDI<0x2D, MRMSrcReg, (outs GR32:$dst), (ins VR128:$src), @@ -3232,7 +3232,7 @@ multiclass sse41_fp_unop_rm<bits<8> opcps, bits<8> opcpd, [(set VR128:$dst, (V4F32Int (memopv4f32 addr:$src1),imm:$src2))]>, TA, OpSize, - Requires<[HasSSE41, NoSSEBreakDep]>; + Requires<[HasSSE41]>; // Vector intrinsic operation, reg def PDr_Int : SS4AIi8<opcpd, MRMSrcReg, |