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| author | Eric Christopher <echristo@apple.com> | 2009-08-08 21:55:08 +0000 |
|---|---|---|
| committer | Eric Christopher <echristo@apple.com> | 2009-08-08 21:55:08 +0000 |
| commit | b4dc13cab7ef894d3bb17657fa993b9f09af476b (patch) | |
| tree | da5ce7301c16bef88ac50c36ac202f859e416c20 /lib/Target/X86/X86InstrSSE.td | |
| parent | 46151de6a0d08184c1bfc90bb39657ff1e21729e (diff) | |
| download | external_llvm-b4dc13cab7ef894d3bb17657fa993b9f09af476b.zip external_llvm-b4dc13cab7ef894d3bb17657fa993b9f09af476b.tar.gz external_llvm-b4dc13cab7ef894d3bb17657fa993b9f09af476b.tar.bz2 | |
Add crc32 instruction and intrinsics. Add a new class of prefix
bytes for F2 0F 38 and propagate. Add a FIXME for a set
of possibilities which correspond to intrinsics already used.
New test.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@78508 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86InstrSSE.td')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 890ebae..fefdba0 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -3678,3 +3678,75 @@ def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, VR128:$src2)), (PCMPGTQrr VR128:$src1, VR128:$src2)>; def : Pat<(v2i64 (X86pcmpgtq VR128:$src1, (memop addr:$src2))), (PCMPGTQrm VR128:$src1, addr:$src2)>; + +// crc intrinsic instruction +// This set of instructions are only rm, the only difference is the size +// of r and m. +let Constraints = "$src1 = $dst" in { + def CRC32m8 : SS42FI<0xF0, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i8mem:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_8 GR32:$src1, + (load addr:$src2)))]>, OpSize; + def CRC32r8 : SS42FI<0xF0, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR8:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>, + OpSize; + def CRC32m16 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i16mem:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_16 GR32:$src1, + (load addr:$src2)))]>, + OpSize; + def CRC32r16 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR16:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_16 GR32:$src1, GR16:$src2))]>, + OpSize; + def CRC32m32 : SS42FI<0xF1, MRMSrcMem, (outs GR32:$dst), + (ins GR32:$src1, i32mem:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_32 GR32:$src1, + (load addr:$src2)))]>, OpSize; + def CRC32r32 : SS42FI<0xF1, MRMSrcReg, (outs GR32:$dst), + (ins GR32:$src1, GR32:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR32:$dst, + (int_x86_sse42_crc32_32 GR32:$src1, GR32:$src2))]>, + OpSize; + def CRC64m64 : SS42FI<0xF0, MRMSrcMem, (outs GR64:$dst), + (ins GR64:$src1, i64mem:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR64:$dst, + (int_x86_sse42_crc32_64 GR64:$src1, + (load addr:$src2)))]>, + OpSize, REX_W; + def CRC64r64 : SS42FI<0xF0, MRMSrcReg, (outs GR64:$dst), + (ins GR64:$src1, GR64:$src2), + "crc32 \t{$src2, $src1|$src1, $src2}", + [(set GR64:$dst, + (int_x86_sse42_crc32_64 GR64:$src1, GR64:$src2))]>, + OpSize, REX_W; + + // TODO: These correspond to int_x86_sse42_crc32_8 but with a 64-bit src + // and dest, figure it out. + //def CRC64m8 : SS42FI<0xF1, MRMSrcMem, (outs GR64:$dst), + // (ins GR32:$src1, i8mem:$src2), + // "crc32 \t{$src2, $src1|$src1, $src2}", + // [(set GR64:$dst, + // (int_x86_sse42_crc32_8 GR64:$src1, + // (load addr:$src2)))]>, + // OpSize, REX_W; + //def CRC64r8 : SS42FI<0xF1, MRMSrcReg, (outs GR64:$dst), + // (ins GR64:$src1, GR8:$src2), + // "crc32 \t{$src2, $src1|$src1, $src2}", + // [(set GR64:$dst, + // (int_x86_sse42_crc32_8 GR32:$src1, GR8:$src2))]>, + // OpSize, REX_W; +} |