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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-08-26 01:02:53 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-08-26 01:02:53 +0000 |
| commit | e943c15621035fa7fbeda7b4922d06a8c2b05b2d (patch) | |
| tree | f4c4536d2c4802a5b1c06b802257cb72cce0a143 /lib/Target/X86/X86MCCodeEmitter.cpp | |
| parent | ae47c6d69e2e34bc558a302586cbc3f27a6d7334 (diff) | |
| download | external_llvm-e943c15621035fa7fbeda7b4922d06a8c2b05b2d.zip external_llvm-e943c15621035fa7fbeda7b4922d06a8c2b05b2d.tar.gz external_llvm-e943c15621035fa7fbeda7b4922d06a8c2b05b2d.tar.bz2 | |
Fix PR7748 without using microsoft extensions
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@112128 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86MCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/X86/X86MCCodeEmitter.cpp | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/lib/Target/X86/X86MCCodeEmitter.cpp b/lib/Target/X86/X86MCCodeEmitter.cpp index 6065483..9564fe0 100644 --- a/lib/Target/X86/X86MCCodeEmitter.cpp +++ b/lib/Target/X86/X86MCCodeEmitter.cpp @@ -365,7 +365,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, const TargetInstrDesc &Desc, raw_ostream &OS) const { bool HasVEX_4V = false; - if (TSFlags & X86II::VEX_4V) + if ((TSFlags >> 32) & X86II::VEX_4V) HasVEX_4V = true; // VEX_R: opcode externsion equivalent to REX.R in @@ -429,10 +429,10 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, if (TSFlags & X86II::OpSize) VEX_PP = 0x01; - if (TSFlags & X86II::VEX_W) + if ((TSFlags >> 32) & X86II::VEX_W) VEX_W = 1; - if (TSFlags & X86II::VEX_L) + if ((TSFlags >> 32) & X86II::VEX_L) VEX_L = 1; switch (TSFlags & X86II::Op0Mask) { @@ -501,7 +501,7 @@ void X86MCCodeEmitter::EmitVEXOpcodePrefix(uint64_t TSFlags, unsigned &CurByte, // If the last register should be encoded in the immediate field // do not use any bit from VEX prefix to this register, ignore it - if (TSFlags & X86II::VEX_I8IMM) + if ((TSFlags >> 32) & X86II::VEX_I8IMM) NumOps--; for (; CurOp != NumOps; ++CurOp) { @@ -801,9 +801,9 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, // It uses the VEX.VVVV field? bool HasVEX_4V = false; - if (TSFlags & X86II::VEX) + if ((TSFlags >> 32) & X86II::VEX) HasVEXPrefix = true; - if (TSFlags & X86II::VEX_4V) + if ((TSFlags >> 32) & X86II::VEX_4V) HasVEX_4V = true; // Determine where the memory operand starts, if present. @@ -955,7 +955,7 @@ EncodeInstruction(const MCInst &MI, raw_ostream &OS, if (CurOp != NumOps) { // The last source register of a 4 operand instruction in AVX is encoded // in bits[7:4] of a immediate byte, and bits[3:0] are ignored. - if (TSFlags & X86II::VEX_I8IMM) { + if ((TSFlags >> 32) & X86II::VEX_I8IMM) { const MCOperand &MO = MI.getOperand(CurOp++); bool IsExtReg = X86InstrInfo::isX86_64ExtendedReg(MO.getReg()); |