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| author | Daniel Dunbar <daniel@zuster.org> | 2010-10-08 02:07:26 +0000 |
|---|---|---|
| committer | Daniel Dunbar <daniel@zuster.org> | 2010-10-08 02:07:26 +0000 |
| commit | 32f0cdba302d5f48401aadb9a2eb9e3efd9e6833 (patch) | |
| tree | c5f70d2d6eddb0b755fe6aac34964f161ed6c8bd /lib/Target/X86/X86MCInstLower.cpp | |
| parent | 6aa526bf76ba74b79ebf4d96d2c1f12d59067530 (diff) | |
| download | external_llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.zip external_llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.tar.gz external_llvm-32f0cdba302d5f48401aadb9a2eb9e3efd9e6833.tar.bz2 | |
Revert "reimplement the second half of the or/add optimization. We should now",
which depends on r116007, which I am about to revert.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116031 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86MCInstLower.cpp')
| -rw-r--r-- | lib/Target/X86/X86MCInstLower.cpp | 12 |
1 files changed, 3 insertions, 9 deletions
diff --git a/lib/Target/X86/X86MCInstLower.cpp b/lib/Target/X86/X86MCInstLower.cpp index 8f90d87..662717b 100644 --- a/lib/Target/X86/X86MCInstLower.cpp +++ b/lib/Target/X86/X86MCInstLower.cpp @@ -437,15 +437,9 @@ ReSimplify: // These are pseudo-ops for OR to help with the OR->ADD transformation. We do // this with an ugly goto in case the resultant OR uses EAX and needs the // short form. - case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; - case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; - case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; - case X86::ADD16ri_DB: OutMI.setOpcode(X86::OR16ri); goto ReSimplify; - case X86::ADD32ri_DB: OutMI.setOpcode(X86::OR32ri); goto ReSimplify; - case X86::ADD64ri32_DB: OutMI.setOpcode(X86::OR64ri32); goto ReSimplify; - case X86::ADD16ri8_DB: OutMI.setOpcode(X86::OR16ri8); goto ReSimplify; - case X86::ADD32ri8_DB: OutMI.setOpcode(X86::OR32ri8); goto ReSimplify; - case X86::ADD64ri8_DB: OutMI.setOpcode(X86::OR64ri8); goto ReSimplify; + case X86::ADD16rr_DB: OutMI.setOpcode(X86::OR16rr); goto ReSimplify; + case X86::ADD32rr_DB: OutMI.setOpcode(X86::OR32rr); goto ReSimplify; + case X86::ADD64rr_DB: OutMI.setOpcode(X86::OR64rr); goto ReSimplify; // The assembler backend wants to see branches in their small form and relax // them to their large form. The JIT can only handle the large form because |