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author | Chris Lattner <sabre@nondot.org> | 2006-02-02 20:12:32 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2006-02-02 20:12:32 +0000 |
commit | 408396014742a05cad1c91949d2226169e3f9d80 (patch) | |
tree | bcd6c4a3a88b934ee998a89cdf6a7ec1d9b03bf7 /lib/Target/X86/X86RegisterInfo.cpp | |
parent | af9fa2bd0c1ee25f3adda96b3e5d7129fbab393a (diff) | |
download | external_llvm-408396014742a05cad1c91949d2226169e3f9d80.zip external_llvm-408396014742a05cad1c91949d2226169e3f9d80.tar.gz external_llvm-408396014742a05cad1c91949d2226169e3f9d80.tar.bz2 |
Move isLoadFrom/StoreToStackSlot from MRegisterInfo to TargetInstrInfo,a far more logical place. Other methods should also be moved if anyoneis interested. :)
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25913 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.cpp')
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 46 |
1 files changed, 0 insertions, 46 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1c0ec8b..ceb0f3f 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -116,52 +116,6 @@ void X86RegisterInfo::copyRegToReg(MachineBasicBlock &MBB, BuildMI(MBB, MI, Opc, 1, DestReg).addReg(SrcReg); } -unsigned X86RegisterInfo::isLoadFromStackSlot(MachineInstr *MI, - int &FrameIndex) const { - switch (MI->getOpcode()) { - default: break; - case X86::MOV8rm: - case X86::MOV16rm: - case X86::MOV32rm: - case X86::FpLD64m: - case X86::MOVSSrm: - case X86::MOVSDrm: - if (MI->getOperand(1).isFrameIndex() && MI->getOperand(2).isImmediate() && - MI->getOperand(3).isRegister() && MI->getOperand(4).isImmediate() && - MI->getOperand(2).getImmedValue() == 1 && - MI->getOperand(3).getReg() == 0 && - MI->getOperand(4).getImmedValue() == 0) { - FrameIndex = MI->getOperand(1).getFrameIndex(); - return MI->getOperand(0).getReg(); - } - break; - } - return 0; -} - -unsigned X86RegisterInfo::isStoreToStackSlot(MachineInstr *MI, - int &FrameIndex) const { - switch (MI->getOpcode()) { - default: break; - case X86::MOV8mr: - case X86::MOV16mr: - case X86::MOV32mr: - case X86::FpSTP64m: - case X86::MOVSSmr: - case X86::MOVSDmr: - if (MI->getOperand(0).isFrameIndex() && MI->getOperand(1).isImmediate() && - MI->getOperand(2).isRegister() && MI->getOperand(3).isImmediate() && - MI->getOperand(3).getImmedValue() == 1 && - MI->getOperand(4).getReg() == 0 && - MI->getOperand(5).getImmedValue() == 0) { - FrameIndex = MI->getOperand(1).getFrameIndex(); - return MI->getOperand(4).getReg(); - } - break; - } - return 0; -} - static MachineInstr *MakeMInst(unsigned Opcode, unsigned FrameIndex, MachineInstr *MI) { |