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author | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-04-26 18:52:33 +0000 |
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committer | Jakob Stoklund Olesen <stoklund@2pi.dk> | 2011-04-26 18:52:33 +0000 |
commit | c9e5015dece0a1a73bec358e11bc87594831279d (patch) | |
tree | 2536ec8e3e79a76982d4f03238684978ea691682 /lib/Target/X86/X86RegisterInfo.cpp | |
parent | efa81404a52020652c4c06499acc29af547b1392 (diff) | |
download | external_llvm-c9e5015dece0a1a73bec358e11bc87594831279d.zip external_llvm-c9e5015dece0a1a73bec358e11bc87594831279d.tar.gz external_llvm-c9e5015dece0a1a73bec358e11bc87594831279d.tar.bz2 |
Add a TRI::getLargestLegalSuperClass hook to provide an upper limit on register class inflation.
The hook will be used by the register allocator when recomputing register
classes after removing constraints.
Thumb1 code doesn't allow anything larger than tGPR, and x86 needs to ensure
that the spill size doesn't change.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@130228 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86RegisterInfo.cpp')
-rw-r--r-- | lib/Target/X86/X86RegisterInfo.cpp | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 40b65e1..37fb0fe 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -308,6 +308,33 @@ X86RegisterInfo::getMatchingSuperRegClass(const TargetRegisterClass *A, return 0; } +const TargetRegisterClass* +X86RegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC) const{ + const TargetRegisterClass *Super = RC; + TargetRegisterClass::sc_iterator I = RC->superclasses_begin(); + do { + switch (Super->getID()) { + case X86::GR8RegClassID: + case X86::GR16RegClassID: + case X86::GR32RegClassID: + case X86::GR64RegClassID: + case X86::FR32RegClassID: + case X86::FR64RegClassID: + case X86::RFP32RegClassID: + case X86::RFP64RegClassID: + case X86::RFP80RegClassID: + case X86::VR128RegClassID: + case X86::VR256RegClassID: + // Don't return a super-class that would shrink the spill size. + // That can happen with the vector and float classes. + if (Super->getSize() == RC->getSize()) + return Super; + } + Super = *I++; + } while (Super); + return RC; +} + const TargetRegisterClass * X86RegisterInfo::getPointerRegClass(unsigned Kind) const { switch (Kind) { |