Extend InlineAsm::C_Register to allow multiple specific registers

(actually, code already all worked, only the comment
changed).  Use this to implement 'A' constraint on x86.
Fixes PR 1779.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59266 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 21 insertions, 0 deletions

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 5228b76..4ddec00 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -440,6 +440,27 @@ def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
   let SubRegClassList = [GR8, GR16];
 }
 
+// A class to support the 'A' assembler constraint: EAX then EDX.
+def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
+  let MethodProtos = [{
+    iterator allocation_order_begin(const MachineFunction &MF) const;
+    iterator allocation_order_end(const MachineFunction &MF) const;
+  }];
+  
+  let MethodBodies = [{
+     static const unsigned X86_GRAD_AO[] = {X86::EAX, X86::EDX};
+   GRADClass::iterator
+    GRADClass::allocation_order_begin(const MachineFunction &MF) const {
+      return X86_GRAD_AO;
+    }
+
+    GRADClass::iterator
+    GRADClass::allocation_order_end(const MachineFunction &MF) const {
+      return X86_GRAD_AO + (sizeof(X86_GRAD_AO) / sizeof(unsigned));
+    }
+  }];
+}
+
 // Scalar SSE2 floating point registers.
 def FR32 : RegisterClass<"X86", [f32], 32,
                          [XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7,