Remove unneeded stuff from GRAD register class.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@59311 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 1 insertions, 19 deletions

diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index 4ddec00..5097b4f 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -441,25 +441,7 @@ def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
 }
 
 // A class to support the 'A' assembler constraint: EAX then EDX.
-def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]> {
-  let MethodProtos = [{
-    iterator allocation_order_begin(const MachineFunction &MF) const;
-    iterator allocation_order_end(const MachineFunction &MF) const;
-  }];
-  
-  let MethodBodies = [{
-     static const unsigned X86_GRAD_AO[] = {X86::EAX, X86::EDX};
-   GRADClass::iterator
-    GRADClass::allocation_order_begin(const MachineFunction &MF) const {
-      return X86_GRAD_AO;
-    }
-
-    GRADClass::iterator
-    GRADClass::allocation_order_end(const MachineFunction &MF) const {
-      return X86_GRAD_AO + (sizeof(X86_GRAD_AO) / sizeof(unsigned));
-    }
-  }];
-}
+def GRAD : RegisterClass<"X86", [i32], 32, [EAX, EDX]>;
 
 // Scalar SSE2 floating point registers.
 def FR32 : RegisterClass<"X86", [f32], 32,