X86 itinerary properties.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8

1 files changed, 23 insertions, 1 deletions

diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td
index f670f28..4331cf3 100644
--- a/lib/Target/X86/X86Schedule.td
+++ b/lib/Target/X86/X86Schedule.td
@@ -456,6 +456,28 @@ def IIC_NOP : InstrItinClass;
 //===----------------------------------------------------------------------===//
 // Processor instruction itineraries.
 
-def GenericItineraries : ProcessorItineraries<[], [], []>;
+// IssueWidth is analagous to the number of decode units. Core and its
+// descendents, including Nehalem and SandyBridge have 4 decoders.
+// Resources beyond the decoder operate on micro-ops and are bufferred
+// so adjacent micro-ops don't directly compete.
+//
+// MinLatency=0 indicates that RAW dependencies can be decoded in the
+// same cycle.
+//
+// HighLatency=10 is optimistic. X86InstrInfo::isHighLatencyDef
+// indicates high latency opcodes. Alternatively, InstrItinData
+// entries may be included here to define specific operand
+// latencies. Since these latencies are not used for pipeline hazards,
+// they do not need to be exact.
+//
+// This set of instruction itineraries should contain no reference to
+// InstrStages. When an iterary has no stages, the scheduler can
+// bypass the logic needed for checking pipeline stage hazards.
+def GenericItineraries : MultiIssueItineraries<
+  4, // IssueWidth
+  0, // MinLatency
+  4, // LoadLatency (expected, may be overriden by OperandCycles)
+ 10, // HighLatency (expected, may be overriden by OperandCycles)
+ [], [], []>; // no FuncUnits, Bypasses, or InstrItinData.
 
 include "X86ScheduleAtom.td"