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| author | Preston Gurd <preston.gurd@intel.com> | 2013-05-07 19:57:34 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2013-05-07 19:57:34 +0000 |
| commit | acccd2edc8d4c078aa03c4dd43ef815087176ef9 (patch) | |
| tree | 0389e90bd50ae3a1e89ba3dda8151e4f53bb5edf /lib/Target/X86/X86Schedule.td | |
| parent | f931f691ee23d431135481fcf23a58658824ca67 (diff) | |
| download | external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.zip external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.tar.gz external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.tar.bz2 | |
Corrected Atom latencies for SSE SQRT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Schedule.td')
| -rw-r--r-- | lib/Target/X86/X86Schedule.td | 12 |
1 files changed, 8 insertions, 4 deletions
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td index 9fbde88..9f2c781 100644 --- a/lib/Target/X86/X86Schedule.td +++ b/lib/Target/X86/X86Schedule.td @@ -266,10 +266,14 @@ def IIC_SSE_PINSRW : InstrItinClass; def IIC_SSE_PABS_RR : InstrItinClass; def IIC_SSE_PABS_RM : InstrItinClass; -def IIC_SSE_SQRTP_RR : InstrItinClass; -def IIC_SSE_SQRTP_RM : InstrItinClass; -def IIC_SSE_SQRTS_RR : InstrItinClass; -def IIC_SSE_SQRTS_RM : InstrItinClass; +def IIC_SSE_SQRTPS_RR : InstrItinClass; +def IIC_SSE_SQRTPS_RM : InstrItinClass; +def IIC_SSE_SQRTSS_RR : InstrItinClass; +def IIC_SSE_SQRTSS_RM : InstrItinClass; +def IIC_SSE_SQRTPD_RR : InstrItinClass; +def IIC_SSE_SQRTPD_RM : InstrItinClass; +def IIC_SSE_SQRTSD_RR : InstrItinClass; +def IIC_SSE_SQRTSD_RM : InstrItinClass; def IIC_SSE_RCPP_RR : InstrItinClass; def IIC_SSE_RCPP_RM : InstrItinClass; |