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| author | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:46 +0000 |
|---|---|---|
| committer | Andrew Trick <atrick@apple.com> | 2012-06-05 03:44:46 +0000 |
| commit | 1d98530196feee3b1b3ddcd793377b9b430a411e (patch) | |
| tree | a9761b4c5e36efa1c638d35d662a2c2f49d636b3 /lib/Target/X86/X86ScheduleAtom.td | |
| parent | f94f051cf5bb2ffbe08f42d1ad6646c900ed6aaa (diff) | |
| download | external_llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.zip external_llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.tar.gz external_llvm-1d98530196feee3b1b3ddcd793377b9b430a411e.tar.bz2 | |
X86 itinerary properties.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157981 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ScheduleAtom.td')
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 7 |
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 81530b5..56dd340 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -22,7 +22,12 @@ def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA // SIMD/FP: SIMD ALU, FP Adder -def AtomItineraries : ProcessorItineraries< +def AtomItineraries : MultiIssueItineraries< + 2, // IssueWidth=2 allows 2 instructions per scheduling group. + 1, // MinLatency=1. InstrStage cycles overrides MinLatency. + // OperandCycles may be used for expected latency. + 3, // LoadLatency (expected, may be overriden by OperandCycles) + 30,// HighLatency (expected, may be overriden by OperandCycles) [ Port0, Port1 ], [], [ // P0 only |