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| author | Preston Gurd <preston.gurd@intel.com> | 2012-03-19 14:10:12 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2012-03-19 14:10:12 +0000 |
| commit | 3e99b715d1f9fd3db9ee3847d845e2804bd82280 (patch) | |
| tree | 0b54ed3d5687b608f766bb41b9a3cc507e518027 /lib/Target/X86/X86ScheduleAtom.td | |
| parent | 8118c94a55b7e3d6bcd43b4a043c922d8e20a8aa (diff) | |
| download | external_llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.zip external_llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.tar.gz external_llvm-3e99b715d1f9fd3db9ee3847d845e2804bd82280.tar.bz2 | |
This patch adds X86 instruction itineraries for non-pseudo opcodes in
X86InstrCompiler.td.
It also adds –mcpu-generic to the legalize-shift-64.ll test so the test
will pass if run on an Intel Atom CPU, which would otherwise
produce an instruction schedule which differs from that which the test expects.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153033 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ScheduleAtom.td')
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 15 |
1 files changed, 13 insertions, 2 deletions
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index e8cf72a..77d4e56 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -144,6 +144,9 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_MOVZX_R16_R8, [InstrStage<2, [Port0, Port1]>] >, InstrItinData<IIC_MOVZX_R16_M8, [InstrStage<3, [Port0, Port1]>] >, + InstrItinData<IIC_REP_MOVS, [InstrStage<75, [Port0, Port1]>] >, + InstrItinData<IIC_REP_STOS, [InstrStage<74, [Port0, Port1]>] >, + // SSE binary operations // arithmetic fp scalar InstrItinData<IIC_SSE_ALU_F32S_RR, [InstrStage<5, [Port1]>] >, @@ -289,6 +292,14 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_SSE_CVT_SS2SI64_RR, [InstrStage<9, [Port0, Port1]>] >, InstrItinData<IIC_SSE_CVT_SS2SI64_RM, [InstrStage<10, [Port0, Port1]>] >, InstrItinData<IIC_SSE_CVT_SD2SI_RR, [InstrStage<8, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] > -]>; + InstrItinData<IIC_SSE_CVT_SD2SI_RM, [InstrStage<9, [Port0, Port1]>] >, + + InstrItinData<IIC_CMPX_LOCK, [InstrStage<14, [Port0, Port1]>] >, + InstrItinData<IIC_CMPX_LOCK_8, [InstrStage<6, [Port0, Port1]>] >, + InstrItinData<IIC_CMPX_LOCK_8B, [InstrStage<18, [Port0, Port1]>] >, + InstrItinData<IIC_CMPX_LOCK_16B, [InstrStage<22, [Port0, Port1]>] >, + + InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<2, [Port0, Port1]>] >, + InstrItinData<IIC_XADD_LOCK_MEM, [InstrStage<3, [Port0, Port1]>] > + ]>; |