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| author | Preston Gurd <preston.gurd@intel.com> | 2013-05-07 19:57:34 +0000 |
|---|---|---|
| committer | Preston Gurd <preston.gurd@intel.com> | 2013-05-07 19:57:34 +0000 |
| commit | acccd2edc8d4c078aa03c4dd43ef815087176ef9 (patch) | |
| tree | 0389e90bd50ae3a1e89ba3dda8151e4f53bb5edf /lib/Target/X86/X86ScheduleAtom.td | |
| parent | f931f691ee23d431135481fcf23a58658824ca67 (diff) | |
| download | external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.zip external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.tar.gz external_llvm-acccd2edc8d4c078aa03c4dd43ef815087176ef9.tar.bz2 | |
Corrected Atom latencies for SSE SQRT instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@181346 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86ScheduleAtom.td')
| -rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index cce8f1b..cb0960a 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -211,10 +211,15 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >, - InstrItinData<IIC_SSE_SQRTP_RR, [InstrStage<13, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_SQRTP_RM, [InstrStage<14, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_SQRTS_RR, [InstrStage<11, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_SQRTS_RM, [InstrStage<12, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTPS_RR, [InstrStage<70, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTPS_RM, [InstrStage<70, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTSS_RR, [InstrStage<34, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTSS_RM, [InstrStage<34, [Port0, Port1]>] >, + + InstrItinData<IIC_SSE_SQRTPD_RR, [InstrStage<125, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTPD_RM, [InstrStage<125, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTSD_RR, [InstrStage<62, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_SQRTSD_RM, [InstrStage<62, [Port0, Port1]>] >, InstrItinData<IIC_SSE_RCPP_RR, [InstrStage<9, [Port0, Port1]>] >, InstrItinData<IIC_SSE_RCPP_RM, [InstrStage<10, [Port0, Port1]>] >, |