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author | Stephen Hines <srhines@google.com> | 2014-02-11 20:01:10 -0800 |
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committer | Stephen Hines <srhines@google.com> | 2014-02-11 20:01:10 -0800 |
commit | ce9904c6ea8fd669978a8eefb854b330eb9828ff (patch) | |
tree | 2418ee2e96ea220977c8fb74959192036ab5b133 /lib/Target/X86/X86ScheduleAtom.td | |
parent | c27b10b198c1d9e9b51f2303994313ec2778edd7 (diff) | |
parent | dbb832b83351cec97b025b61c26536ef50c3181c (diff) | |
download | external_llvm-ce9904c6ea8fd669978a8eefb854b330eb9828ff.zip external_llvm-ce9904c6ea8fd669978a8eefb854b330eb9828ff.tar.gz external_llvm-ce9904c6ea8fd669978a8eefb854b330eb9828ff.tar.bz2 |
Merge remote-tracking branch 'upstream/release_34' into merge-20140211
Conflicts:
lib/Linker/LinkModules.cpp
lib/Support/Unix/Signals.inc
Change-Id: Ia54f291fa5dc828052d2412736e8495c1282aa64
Diffstat (limited to 'lib/Target/X86/X86ScheduleAtom.td')
-rw-r--r-- | lib/Target/X86/X86ScheduleAtom.td | 24 |
1 files changed, 15 insertions, 9 deletions
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 14a1471..ba72f29 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file defines the itinerary class data for the Intel Atom (Bonnell) -// processors. +// This file defines the itinerary class data for the Intel Atom +// in order (Saltwell-32nm/Bonnell-45nm) processors. // //===----------------------------------------------------------------------===// @@ -79,9 +79,12 @@ def AtomItineraries : ProcessorItineraries< // neg/not/inc/dec InstrItinData<IIC_UNARY_REG, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_UNARY_MEM, [InstrStage<1, [Port0]>] >, - // add/sub/and/or/xor/adc/sbc/cmp/test + // add/sub/and/or/xor/cmp/test InstrItinData<IIC_BIN_NONMEM, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_BIN_MEM, [InstrStage<1, [Port0]>] >, + // adc/sbc + InstrItinData<IIC_BIN_CARRY_NONMEM, [InstrStage<1, [Port0, Port1]>] >, + InstrItinData<IIC_BIN_CARRY_MEM, [InstrStage<1, [Port0]>] >, // shift/rotate InstrItinData<IIC_SR, [InstrStage<1, [Port0]>] >, // shift double @@ -203,11 +206,11 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_SSE_INTSH_P_RM, [InstrStage<3, [Port0, Port1]>] >, InstrItinData<IIC_SSE_INTSH_P_RI, [InstrStage<1, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_CMPP_RR, [InstrStage<6, [Port0, Port1]>] >, - InstrItinData<IIC_SSE_CMPP_RM, [InstrStage<7, [Port0, Port1]>] >, + InstrItinData<IIC_SSE_INTSHDQ_P_RI, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_SSE_SHUFP, [InstrStage<1, [Port0]>] >, - InstrItinData<IIC_SSE_PSHUF, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_SSE_PSHUF_RI, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_SSE_PSHUF_MI, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_SSE_UNPCK, [InstrStage<1, [Port0]>] >, @@ -278,7 +281,8 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_SSE_PMADD, [InstrStage<5, [Port0]>] >, InstrItinData<IIC_SSE_PMULHRSW, [InstrStage<5, [Port0]>] >, - InstrItinData<IIC_SSE_PALIGNR, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_SSE_PALIGNRR, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_SSE_PALIGNRM, [InstrStage<1, [Port0]>] >, InstrItinData<IIC_SSE_MWAIT, [InstrStage<46, [Port0, Port1]>] >, InstrItinData<IIC_SSE_MONITOR, [InstrStage<45, [Port0, Port1]>] >, @@ -470,8 +474,8 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_PUSH_A, [InstrStage<8, [Port0, Port1]>] >, InstrItinData<IIC_BSWAP, [InstrStage<1, [Port0]>] >, - InstrItinData<IIC_BSF, [InstrStage<16, [Port0, Port1]>] >, - InstrItinData<IIC_BSR, [InstrStage<16, [Port0, Port1]>] >, + InstrItinData<IIC_BIT_SCAN_MEM, [InstrStage<16, [Port0, Port1]>] >, + InstrItinData<IIC_BIT_SCAN_REG, [InstrStage<16, [Port0, Port1]>] >, InstrItinData<IIC_MOVS, [InstrStage<3, [Port0, Port1]>] >, InstrItinData<IIC_STOS, [InstrStage<1, [Port0, Port1]>] >, InstrItinData<IIC_SCAS, [InstrStage<2, [Port0, Port1]>] >, @@ -518,6 +522,8 @@ def AtomItineraries : ProcessorItineraries< InstrItinData<IIC_ARPL_REG, [InstrStage<24, [Port0, Port1]>] >, InstrItinData<IIC_ARPL_MEM, [InstrStage<23, [Port0, Port1]>] >, InstrItinData<IIC_MOVBE, [InstrStage<1, [Port0]>] >, + InstrItinData<IIC_CBW, [InstrStage<4, [Port0, Port1]>] >, + InstrItinData<IIC_MMX_EMMS, [InstrStage<5, [Port0, Port1]>] >, InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] > ]>; |