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| author | Ben Langmuir <ben.langmuir@intel.com> | 2013-09-12 15:51:31 +0000 |
|---|---|---|
| committer | Ben Langmuir <ben.langmuir@intel.com> | 2013-09-12 15:51:31 +0000 |
| commit | 1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f (patch) | |
| tree | 6a4093eec10f724f5f8bc99e58474ecfa2ec66e8 /lib/Target/X86/X86Subtarget.h | |
| parent | c0b12dfd0a83081c1ebbb55a89c7a2c1f98f1842 (diff) | |
| download | external_llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.zip external_llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.tar.gz external_llvm-1f1bd9a54d25d4e2c5da13c2cae7fa5e3d8acc9f.tar.bz2 | |
Partial support for Intel SHA Extensions (sha1rnds4)
Add basic assembly/disassembly support for the first Intel SHA
instruction 'sha1rnds4'. Also includes feature flag, and test cases.
Support for the remaining instructions will follow in a separate patch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@190611 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86/X86Subtarget.h')
| -rw-r--r-- | lib/Target/X86/X86Subtarget.h | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/lib/Target/X86/X86Subtarget.h b/lib/Target/X86/X86Subtarget.h index 67b88eb..28aae20 100644 --- a/lib/Target/X86/X86Subtarget.h +++ b/lib/Target/X86/X86Subtarget.h @@ -127,6 +127,9 @@ protected: /// HasADX - Processor has ADX instructions. bool HasADX; + /// HasSHA - Processor has SHA instructions. + bool HasSHA; + /// HasPRFCHW - Processor has PRFCHW instructions. bool HasPRFCHW; @@ -281,6 +284,7 @@ public: bool hasRTM() const { return HasRTM; } bool hasHLE() const { return HasHLE; } bool hasADX() const { return HasADX; } + bool hasSHA() const { return HasSHA; } bool hasPRFCHW() const { return HasPRFCHW; } bool hasRDSEED() const { return HasRDSEED; } bool isBTMemSlow() const { return IsBTMemSlow; } |