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authorNadav Rotem <nadav.rotem@intel.com>2011-03-19 13:09:10 +0000
committerNadav Rotem <nadav.rotem@intel.com>2011-03-19 13:09:10 +0000
commit06cc324b9da1dc8fb7360a560343c28f5e7a940a (patch)
treef055ce6e171c709584dc15a25174178955a37bbf /lib/Target/X86
parent415247dac4cdbec704af6caa69aff2ac63f21377 (diff)
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Add support for legalizing UINT_TO_FP of vectors on platforms which do
not have native support for this operation (such as X86). The legalized code uses two vector INT_TO_FP operations and is faster than scalarizing. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@127951 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp1
1 files changed, 1 insertions, 0 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index a4d01a1..576c879 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -927,6 +927,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// Can turn SHL into an integer multiply.
setOperationAction(ISD::SHL, MVT::v4i32, Custom);
setOperationAction(ISD::SHL, MVT::v16i8, Custom);
+ setOperationAction(ISD::SRL, MVT::v4i32, Legal);
// i8 and i16 vectors are custom , because the source register and source
// source memory operand types are not the same width. f32 vectors are