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| author | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-07-23 00:14:54 +0000 |
|---|---|---|
| committer | Bruno Cardoso Lopes <bruno.cardoso@gmail.com> | 2010-07-23 00:14:54 +0000 |
| commit | 06e6e101a0e71cb8e3f612aaa3549f4750957357 (patch) | |
| tree | b38a68628d4bd33429ce15345bba2890f5064e63 /lib/Target/X86 | |
| parent | 02dee5b437f65d7907702eb91e7d435842375ca2 (diff) | |
| download | external_llvm-06e6e101a0e71cb8e3f612aaa3549f4750957357.zip external_llvm-06e6e101a0e71cb8e3f612aaa3549f4750957357.tar.gz external_llvm-06e6e101a0e71cb8e3f612aaa3549f4750957357.tar.bz2 | |
Fix some AVX instructions which didnt had HasAVX prefix. And also a problem with PINSRW, which was totally wrong because of a typo I introduced previously
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@109198 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 14 |
1 files changed, 8 insertions, 6 deletions
diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 75c1b2c..0e69105 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2729,15 +2729,15 @@ def PEXTRWri : PDIi8<0xC5, MRMSrcReg, // Insert let isAsmParserOnly = 1, Predicates = [HasAVX] in { - defm PINSRW : sse2_pinsrw<0>, OpSize, VEX_4V; - def PINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), + defm VPINSRW : sse2_pinsrw<0>, OpSize, VEX_4V; + def VPINSRWrr64i : Ii8<0xC4, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src1, GR64:$src2, i32i8imm:$src3), "vpinsrw\t{$src3, $src2, $src1, $dst|$dst, $src1, $src2, $src3}", []>, OpSize, VEX_4V; } let Constraints = "$src1 = $dst" in - defm VPINSRW : sse2_pinsrw, TB, OpSize; + defm PINSRW : sse2_pinsrw, TB, OpSize, Requires<[HasSSE2]>; } // ExeDomain = SSEPackedInt @@ -3026,7 +3026,7 @@ def VMOVQd64rr_alt : VPDI<0x7E, MRMDestReg, (outs GR64:$dst), (ins VR128:$src), // xr = XMM register // xm = mem64 -let isAsmParserOnly = 1 in +let isAsmParserOnly = 1, Predicates = [HasAVX] in def VMOVQxrxr: I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), "vmovq\t{$src, $dst|$dst, $src}", []>, VEX, XS; def MOVQxrxr : I<0x7E, MRMSrcReg, (outs VR128:$dst), (ins VR128:$src), @@ -5213,9 +5213,11 @@ def VPERM2F128rm : AVXAIi8<0x06, MRMSrcMem, (outs VR256:$dst), []>, VEX_4V; // Zero All YMM registers -def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L; +def VZEROALL : I<0x77, RawFrm, (outs), (ins), "vzeroall", []>, VEX, VEX_L, + Requires<[HasAVX]>; // Zero Upper bits of YMM registers -def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX; +def VZEROUPPER : I<0x77, RawFrm, (outs), (ins), "vzeroupper", []>, VEX, + Requires<[HasAVX]>; } // isAsmParserOnly |