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| author | Evan Cheng <evan.cheng@apple.com> | 2006-01-20 01:13:30 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2006-01-20 01:13:30 +0000 |
| commit | 21d544393480c7cfadf9a7c389be1b99d5017440 (patch) | |
| tree | 1c7065b2570b4b40dea8b621f2c020e7f989e755 /lib/Target/X86 | |
| parent | 52b8b5982f8e795ebf89c289619d1feee13cf63f (diff) | |
| download | external_llvm-21d544393480c7cfadf9a7c389be1b99d5017440.zip external_llvm-21d544393480c7cfadf9a7c389be1b99d5017440.tar.gz external_llvm-21d544393480c7cfadf9a7c389be1b99d5017440.tar.bz2 | |
A few more SH{L|R}D peepholes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25473 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 16 | ||||
| -rw-r--r-- | lib/Target/X86/X86TargetMachine.cpp | 2 |
2 files changed, 17 insertions, 1 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 92b0c96..b60292e 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -3073,17 +3073,33 @@ def : Pat<(or (srl R32:$src1, CL:$amt), (shl R32:$src2, (sub 32, CL:$amt))), (SHRD32rrCL R32:$src1, R32:$src2)>; +def : Pat<(store (or (srl (loadi32 addr:$dst), CL:$amt), + (shl R32:$src2, (sub 32, CL:$amt))), addr:$dst), + (SHRD32mrCL addr:$dst, R32:$src2)>; + // (or (x << c) | (y >> (32 - c))) ==> (shld32 x, y, c) def : Pat<(or (shl R32:$src1, CL:$amt), (srl R32:$src2, (sub 32, CL:$amt))), (SHLD32rrCL R32:$src1, R32:$src2)>; +def : Pat<(store (or (shl (loadi32 addr:$dst), CL:$amt), + (srl R32:$src2, (sub 32, CL:$amt))), addr:$dst), + (SHLD32mrCL addr:$dst, R32:$src2)>; + // (or (x >> c) | (y << (16 - c))) ==> (shrd16 x, y, c) def : Pat<(or (srl R16:$src1, CL:$amt), (shl R16:$src2, (sub 16, CL:$amt))), (SHRD16rrCL R16:$src1, R16:$src2)>; +def : Pat<(store (or (srl (loadi16 addr:$dst), CL:$amt), + (shl R16:$src2, (sub 16, CL:$amt))), addr:$dst), + (SHRD16mrCL addr:$dst, R16:$src2)>; + // (or (x << c) | (y >> (16 - c))) ==> (shld16 x, y, c) def : Pat<(or (shl R16:$src1, CL:$amt), (srl R16:$src2, (sub 16, CL:$amt))), (SHLD16rrCL R16:$src1, R16:$src2)>; + +def : Pat<(store (or (shl (loadi16 addr:$dst), CL:$amt), + (srl R16:$src2, (sub 16, CL:$amt))), addr:$dst), + (SHLD16mrCL addr:$dst, R16:$src2)>; diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index 4af0b06..a484b9d 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -48,7 +48,7 @@ namespace { cl::opt<bool, true> EnableX86DAGDAG("enable-x86-dag-isel", cl::Hidden, cl::desc("Enable DAG-to-DAG isel for X86"), cl::location(X86DAGIsel), - cl::init(false)); + cl::init(true)); // FIXME: This should eventually be handled with target triples and // subtarget support! |