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author | Chris Lattner <sabre@nondot.org> | 2005-01-19 07:11:01 +0000 |
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committer | Chris Lattner <sabre@nondot.org> | 2005-01-19 07:11:01 +0000 |
commit | 41e431ba045eb317ebf0ec45b563a5d96c212f5c (patch) | |
tree | 4269a38badc0912d3398aa99fb717578c4316df4 /lib/Target/X86 | |
parent | c71d6949b91e19610f0f85f57b402b4df43019a5 (diff) | |
download | external_llvm-41e431ba045eb317ebf0ec45b563a5d96c212f5c.zip external_llvm-41e431ba045eb317ebf0ec45b563a5d96c212f5c.tar.gz external_llvm-41e431ba045eb317ebf0ec45b563a5d96c212f5c.tar.bz2 |
Teach the code generator that shrd/shld is commutable if it has an immediate.
This allows us to generate this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %EDX, DWORD PTR [%ESP + 8]
shld %EDX, %EDX, 2
shl %EAX, 2
ret
instead of this:
foo:
mov %EAX, DWORD PTR [%ESP + 4]
mov %ECX, DWORD PTR [%ESP + 8]
mov %EDX, %EAX
shrd %EDX, %ECX, 30
shl %EAX, 2
ret
Note the magically transmogrifying immediate.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@19686 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
-rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 20 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.h | 6 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 3 |
3 files changed, 29 insertions, 0 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index a13498e..9d304b5 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -121,6 +121,26 @@ MachineInstr *X86InstrInfo::convertToThreeAddress(MachineInstr *MI) const { return 0; } +/// commuteInstruction - We have a few instructions that must be hacked on to +/// commute them. +/// +MachineInstr *X86InstrInfo::commuteInstruction(MachineInstr *MI) const { + switch (MI->getOpcode()) { + case X86::SHRD32rri8: // A = SHRD32rri8 B, C, I -> A = SHLD32rri8 C, B, (32-I) + case X86::SHLD32rri8:{// A = SHLD32rri8 B, C, I -> A = SHRD32rri8 C, B, (32-I) + unsigned Amt = MI->getOperand(3).getImmedValue(); + unsigned A = MI->getOperand(0).getReg(); + unsigned B = MI->getOperand(1).getReg(); + unsigned C = MI->getOperand(2).getReg(); + unsigned Opc = X86::SHRD32rri8; + if (MI->getOpcode() == X86::SHRD32rri8) Opc = X86::SHLD32rri8; + return BuildMI(Opc, 3, A).addReg(B).addReg(C).addImm(32-Amt); + } + default: + return TargetInstrInfo::commuteInstruction(MI); + } +} + void X86InstrInfo::insertGoto(MachineBasicBlock& MBB, MachineBasicBlock& TMBB) const { diff --git a/lib/Target/X86/X86InstrInfo.h b/lib/Target/X86/X86InstrInfo.h index c8f8716..f185569 100644 --- a/lib/Target/X86/X86InstrInfo.h +++ b/lib/Target/X86/X86InstrInfo.h @@ -191,6 +191,12 @@ public: /// virtual MachineInstr *convertToThreeAddress(MachineInstr *TA) const; + /// commuteInstruction - We have a few instructions that must be hacked on to + /// commute them. + /// + virtual MachineInstr *commuteInstruction(MachineInstr *MI) const; + + /// Insert a goto (unconditional branch) sequence to TMBB, at the /// end of MBB virtual void insertGoto(MachineBasicBlock& MBB, diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index dc9afa3..d50133b 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -881,12 +881,15 @@ def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, Imp<[CL],[]>, TB; + +let isCommutable = 1 in { // These instructions commute to each other. def SHLD32rri8 : Ii8<0xA4, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; def SHRD32rri8 : Ii8<0xAC, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; +} let isTwoAddress = 0 in { def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), |