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| author | Chris Lattner <sabre@nondot.org> | 2003-11-18 17:47:05 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2003-11-18 17:47:05 +0000 |
| commit | 62b767b8d7b8ab9758af0a221e9071b118865468 (patch) | |
| tree | 3a99ca73a576346bae8da8aea78a884046daba8f /lib/Target/X86 | |
| parent | 76c1e380395abd608fd3a1e8f9835b21d1b5e081 (diff) | |
| download | external_llvm-62b767b8d7b8ab9758af0a221e9071b118865468.zip external_llvm-62b767b8d7b8ab9758af0a221e9071b118865468.tar.gz external_llvm-62b767b8d7b8ab9758af0a221e9071b118865468.tar.bz2 | |
Fix PR123
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@10069 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/InstSelectSimple.cpp | 14 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelSimple.cpp | 14 |
2 files changed, 14 insertions, 14 deletions
diff --git a/lib/Target/X86/InstSelectSimple.cpp b/lib/Target/X86/InstSelectSimple.cpp index de341c4..1616ec1 100644 --- a/lib/Target/X86/InstSelectSimple.cpp +++ b/lib/Target/X86/InstSelectSimple.cpp @@ -1375,7 +1375,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, switch (Class) { case cFP: // Floating point divide if (isDiv) { - BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); + BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); } else { // Floating point remainder... MachineInstr *TheCall = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true); @@ -1420,26 +1420,26 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, unsigned ExtReg = ExtRegs[Class]; // Put the first operand into one of the A registers... - BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg); if (isSigned) { // Emit a sign extension instruction... unsigned ShiftResult = makeAnotherReg(Ty); - BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); - BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); + BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); + BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) - BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); + BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } // Emit the appropriate divide or remainder instruction... - BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); + BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); // Figure out which register we want to pick the result out of... unsigned DestReg = isDiv ? Reg : ExtReg; // Put the result into the destination register... - BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg); + BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg); } diff --git a/lib/Target/X86/X86ISelSimple.cpp b/lib/Target/X86/X86ISelSimple.cpp index de341c4..1616ec1 100644 --- a/lib/Target/X86/X86ISelSimple.cpp +++ b/lib/Target/X86/X86ISelSimple.cpp @@ -1375,7 +1375,7 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, switch (Class) { case cFP: // Floating point divide if (isDiv) { - BuildMI(BB, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); + BMI(BB, IP, X86::FpDIV, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg); } else { // Floating point remainder... MachineInstr *TheCall = BuildMI(X86::CALLpcrel32, 1).addExternalSymbol("fmod", true); @@ -1420,26 +1420,26 @@ void ISel::emitDivRemOperation(MachineBasicBlock *BB, unsigned ExtReg = ExtRegs[Class]; // Put the first operand into one of the A registers... - BuildMI(BB, MovOpcode[Class], 1, Reg).addReg(Op0Reg); + BMI(BB, IP, MovOpcode[Class], 1, Reg).addReg(Op0Reg); if (isSigned) { // Emit a sign extension instruction... unsigned ShiftResult = makeAnotherReg(Ty); - BuildMI(BB, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); - BuildMI(BB, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); + BMI(BB, IP, SarOpcode[Class], 2, ShiftResult).addReg(Op0Reg).addZImm(31); + BMI(BB, IP, MovOpcode[Class], 1, ExtReg).addReg(ShiftResult); } else { // If unsigned, emit a zeroing instruction... (reg = xor reg, reg) - BuildMI(BB, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); + BMI(BB, IP, ClrOpcode[Class], 2, ExtReg).addReg(ExtReg).addReg(ExtReg); } // Emit the appropriate divide or remainder instruction... - BuildMI(BB, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); + BMI(BB, IP, DivOpcode[isSigned][Class], 1).addReg(Op1Reg); // Figure out which register we want to pick the result out of... unsigned DestReg = isDiv ? Reg : ExtReg; // Put the result into the destination register... - BuildMI(BB, MovOpcode[Class], 1, ResultReg).addReg(DestReg); + BMI(BB, IP, MovOpcode[Class], 1, ResultReg).addReg(DestReg); } |