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author | Eric Christopher <echristo@apple.com> | 2010-08-13 02:37:50 +0000 |
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committer | Eric Christopher <echristo@apple.com> | 2010-08-13 02:37:50 +0000 |
commit | 63f02ac34951958019bcbc54ae5fb0f4b12118f3 (patch) | |
tree | f733aa08508ac9e23353ac022777977f7697c1a8 /lib/Target/X86 | |
parent | 4404c00db6322000d8d80d08d523cca0dc6fffad (diff) | |
download | external_llvm-63f02ac34951958019bcbc54ae5fb0f4b12118f3.zip external_llvm-63f02ac34951958019bcbc54ae5fb0f4b12118f3.tar.gz external_llvm-63f02ac34951958019bcbc54ae5fb0f4b12118f3.tar.bz2 |
Revert last patch and r110954 as I meant to.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@111001 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
-rw-r--r-- | lib/Target/X86/X86CodeEmitter.cpp | 1 | ||||
-rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 47 |
2 files changed, 24 insertions, 24 deletions
diff --git a/lib/Target/X86/X86CodeEmitter.cpp b/lib/Target/X86/X86CodeEmitter.cpp index 84772ea..ef2255d 100644 --- a/lib/Target/X86/X86CodeEmitter.cpp +++ b/lib/Target/X86/X86CodeEmitter.cpp @@ -702,7 +702,6 @@ void Emitter<CodeEmitter>::emitInstruction(const MachineInstr &MI, // base address. switch (Opcode) { default: - MI.dump(); llvm_unreachable("psuedo instructions should be removed before code" " emission"); break; diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index a1a2609..6cddc55 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -2174,33 +2174,33 @@ def : Pat<(X86SFence), (SFENCE)>; // Alias instructions that map zero vector to pxor / xorp* for sse. // We set canFoldAsLoad because this can be converted to a constant-pool // load of an all-zeros value if folding it would be beneficial. +// FIXME: Change encoding to pseudo! let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, isCodeGenOnly = 1 in { - let Predicates = [HasSSE1] in - def V_SET0PS : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4f32 immAllZerosV))]>; - let Predicates = [HasSSE2] in { - def V_SET0PD : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v2f64 immAllZerosV))]>; - def V_SET0PI : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4i32 immAllZerosV))], SSEPackedInt>; - } +def V_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>; +def V_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v2f64 immAllZerosV))]>; +let ExeDomain = SSEPackedInt in +def V_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllZerosV))]>; } // The same as done above but for AVX. The 128-bit versions are the // same, but re-encoded. The 256-bit does not support PI version. let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, isCodeGenOnly = 1, Predicates = [HasAVX] in { -def AVX_SET0PS : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4f32 immAllZerosV))]>; -def AVX_SET0PD : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v2f64 immAllZerosV))]>; -def AVX_SET0PI : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4i32 immAllZerosV))], SSEPackedInt>; -def AVX_SET0PSY : I<0, Pseudo, (outs VR256:$dst), (ins), "", - [(set VR256:$dst, (v8f32 immAllZerosV))]>; -def AVX_SET0PDY : I<0, Pseudo, (outs VR256:$dst), (ins), "", - [(set VR256:$dst, (v4f64 immAllZerosV))]>; +def AVX_SET0PS : PSI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4f32 immAllZerosV))]>, VEX_4V; +def AVX_SET0PD : PDI<0x57, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v2f64 immAllZerosV))]>, VEX_4V; +def AVX_SET0PSY : PSI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V; +def AVX_SET0PDY : PDI<0x57, MRMInitReg, (outs VR256:$dst), (ins), "", + [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V; +let ExeDomain = SSEPackedInt in +def AVX_SET0PI : PDI<0xEF, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllZerosV))]>; } def : Pat<(v2i64 immAllZerosV), (V_SET0PI)>; @@ -3249,13 +3249,14 @@ def : Pat<(X86MFence), (MFENCE)>; // was introduced with SSE2, it's backward compatible. def PAUSE : I<0x90, RawFrm, (outs), (ins), "pause", []>, REP; -// Alias instructions that map one vector to pcmpeqd for sse2 and above. +// Alias instructions that map zero vector to pxor / xorp* for sse. // We set canFoldAsLoad because this can be converted to a constant-pool // load of an all-ones value if folding it would be beneficial. let isReMaterializable = 1, isAsCheapAsAMove = 1, canFoldAsLoad = 1, - isCodeGenOnly = 1, Predicates = [HasSSE2] in - def V_SETALLONES : I<0, Pseudo, (outs VR128:$dst), (ins), "", - [(set VR128:$dst, (v4i32 immAllOnesV))], SSEPackedInt>; + isCodeGenOnly = 1, ExeDomain = SSEPackedInt in + // FIXME: Change encoding to pseudo. + def V_SETALLONES : PDI<0x76, MRMInitReg, (outs VR128:$dst), (ins), "", + [(set VR128:$dst, (v4i32 immAllOnesV))]>; //===---------------------------------------------------------------------===// // SSE3 - Conversion Instructions |