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authorDan Gohman <gohman@apple.com>2009-04-27 16:33:14 +0000
committerDan Gohman <gohman@apple.com>2009-04-27 16:33:14 +0000
commit6e438701fb95c729ae10e42a3faeffba3f70810c (patch)
tree055f50bed9e7d9e11491f4d1cf65235b1a49ff35 /lib/Target/X86
parent70a8a1122a6f9f06767a6ab139b310e3fd5aaccd (diff)
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external_llvm-6e438701fb95c729ae10e42a3faeffba3f70810c.tar.gz
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Rename GR8_, GR16_, GR32_, and GR64_ to GR8_ABCD, GR16_ABCD,
GR32_ABCD, and GR64_ABCD, respectively, to help describe them. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70210 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
-rw-r--r--lib/Target/X86/X86FastISel.cpp4
-rw-r--r--lib/Target/X86/X86Instr64bit.td12
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp24
-rw-r--r--lib/Target/X86/X86InstrInfo.td20
-rw-r--r--lib/Target/X86/X86RegisterInfo.td24
5 files changed, 42 insertions, 42 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 4284456..2a44803 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -996,10 +996,10 @@ bool X86FastISel::X86SelectTrunc(Instruction *I) {
// Unhandled operand. Halt "fast" selection and bail.
return false;
- // First issue a copy to GR16_ or GR32_.
+ // First issue a copy to GR16_ABCD or GR32_ABCD.
unsigned CopyOpc = (SrcVT == MVT::i16) ? X86::MOV16rr : X86::MOV32rr;
const TargetRegisterClass *CopyRC = (SrcVT == MVT::i16)
- ? X86::GR16_RegisterClass : X86::GR32_RegisterClass;
+ ? X86::GR16_ABCDRegisterClass : X86::GR32_ABCDRegisterClass;
unsigned CopyReg = createResultReg(CopyRC);
BuildMI(MBB, DL, TII.get(CopyOpc), CopyReg).addReg(InputReg);
diff --git a/lib/Target/X86/X86Instr64bit.td b/lib/Target/X86/X86Instr64bit.td
index 3084e1c..715eb00 100644
--- a/lib/Target/X86/X86Instr64bit.td
+++ b/lib/Target/X86/X86Instr64bit.td
@@ -1594,18 +1594,18 @@ def : Pat<(and (srl_su GR64:$src, (i8 8)), (i64 255)),
(SUBREG_TO_REG
(i64 0),
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_32bit)>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
def : Pat<(srl_su GR16:$src, (i8 8)),
(EXTRACT_SUBREG
(MOVZX32_NOREXrr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_16bit)>,
Requires<[In64BitMode]>;
@@ -1614,18 +1614,18 @@ def : Pat<(srl_su GR16:$src, (i8 8)),
def : Pat<(store (i8 (trunc_su (srl_su GR64:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR64:$src, GR64_ABCD),
x86_subreg_8bit_hi))>;
def : Pat<(store (i8 (trunc_su (srl_su GR32:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
def : Pat<(store (i8 (trunc_su (srl_su GR16:$src, (i8 8)))), addr:$dst),
(MOV8mr_NOREX
addr:$dst,
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In64BitMode]>;
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp
index d8c0833..e748e11 100644
--- a/lib/Target/X86/X86InstrInfo.cpp
+++ b/lib/Target/X86/X86InstrInfo.cpp
@@ -1681,13 +1681,13 @@ bool X86InstrInfo::copyRegToReg(MachineBasicBlock &MBB,
Opc = X86::MOV8rr_NOREX;
else
Opc = X86::MOV8rr;
- } else if (CommonRC == &X86::GR64_RegClass) {
+ } else if (CommonRC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64rr;
- } else if (CommonRC == &X86::GR32_RegClass) {
+ } else if (CommonRC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32rr;
- } else if (CommonRC == &X86::GR16_RegClass) {
+ } else if (CommonRC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16rr;
- } else if (CommonRC == &X86::GR8_RegClass) {
+ } else if (CommonRC == &X86::GR8_ABCDRegClass) {
Opc = X86::MOV8rr;
} else if (CommonRC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64rr;
@@ -1802,13 +1802,13 @@ static unsigned getStoreRegOpcode(const TargetRegisterClass *RC,
Opc = X86::MOV16mr;
} else if (RC == &X86::GR8RegClass) {
Opc = X86::MOV8mr;
- } else if (RC == &X86::GR64_RegClass) {
+ } else if (RC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64mr;
- } else if (RC == &X86::GR32_RegClass) {
+ } else if (RC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32mr;
- } else if (RC == &X86::GR16_RegClass) {
+ } else if (RC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16mr;
- } else if (RC == &X86::GR8_RegClass) {
+ } else if (RC == &X86::GR8_ABCDRegClass) {
Opc = X86::MOV8mr;
} else if (RC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64mr;
@@ -1882,13 +1882,13 @@ static unsigned getLoadRegOpcode(const TargetRegisterClass *RC,
Opc = X86::MOV16rm;
} else if (RC == &X86::GR8RegClass) {
Opc = X86::MOV8rm;
- } else if (RC == &X86::GR64_RegClass) {
+ } else if (RC == &X86::GR64_ABCDRegClass) {
Opc = X86::MOV64rm;
- } else if (RC == &X86::GR32_RegClass) {
+ } else if (RC == &X86::GR32_ABCDRegClass) {
Opc = X86::MOV32rm;
- } else if (RC == &X86::GR16_RegClass) {
+ } else if (RC == &X86::GR16_ABCDRegClass) {
Opc = X86::MOV16rm;
- } else if (RC == &X86::GR8_RegClass) {
+ } else if (RC == &X86::GR8_ABCDRegClass) {
Opc = X86::MOV8rm;
} else if (RC == &X86::GR64_NOREXRegClass) {
Opc = X86::MOV64rm;
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td
index c8f986a..b01807a 100644
--- a/lib/Target/X86/X86InstrInfo.td
+++ b/lib/Target/X86/X86InstrInfo.td
@@ -3372,12 +3372,12 @@ def : Pat<(and GR32:$src1, 0xffff),
(MOVZX32rr16 (EXTRACT_SUBREG GR32:$src1, x86_subreg_16bit))>;
// r & (2^8-1) ==> movz
def : Pat<(and GR32:$src1, 0xff),
- (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_),
+ (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src1, GR32_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
// r & (2^8-1) ==> movz
def : Pat<(and GR16:$src1, 0xff),
- (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_),
+ (MOVZX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src1, GR16_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
@@ -3385,11 +3385,11 @@ def : Pat<(and GR16:$src1, 0xff),
def : Pat<(sext_inreg GR32:$src, i16),
(MOVSX32rr16 (EXTRACT_SUBREG GR32:$src, x86_subreg_16bit))>;
def : Pat<(sext_inreg GR32:$src, i8),
- (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (MOVSX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
def : Pat<(sext_inreg GR16:$src, i8),
- (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (MOVSX16rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit))>,
Requires<[In32BitMode]>;
@@ -3397,32 +3397,32 @@ def : Pat<(sext_inreg GR16:$src, i8),
def : Pat<(i16 (trunc GR32:$src)),
(EXTRACT_SUBREG GR32:$src, x86_subreg_16bit)>;
def : Pat<(i8 (trunc GR32:$src)),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit)>,
Requires<[In32BitMode]>;
def : Pat<(i8 (trunc GR16:$src)),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit)>,
Requires<[In32BitMode]>;
// h-register tricks
def : Pat<(i8 (trunc (srl_su GR16:$src, (i8 8)))),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(i8 (trunc (srl_su GR32:$src, (i8 8)))),
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi)>,
Requires<[In32BitMode]>;
def : Pat<(srl_su GR16:$src, (i8 8)),
(EXTRACT_SUBREG
(MOVZX32rr8
- (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_),
+ (EXTRACT_SUBREG (COPY_TO_REGCLASS GR16:$src, GR16_ABCD),
x86_subreg_8bit_hi)),
x86_subreg_16bit)>,
Requires<[In32BitMode]>;
def : Pat<(and (srl_su GR32:$src, (i8 8)), (i32 255)),
- (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_),
+ (MOVZX32rr8 (EXTRACT_SUBREG (COPY_TO_REGCLASS GR32:$src, GR32_ABCD),
x86_subreg_8bit_hi))>,
Requires<[In32BitMode]>;
diff --git a/lib/Target/X86/X86RegisterInfo.td b/lib/Target/X86/X86RegisterInfo.td
index a375868..773cba3 100644
--- a/lib/Target/X86/X86RegisterInfo.td
+++ b/lib/Target/X86/X86RegisterInfo.td
@@ -461,21 +461,21 @@ def GR64 : RegisterClass<"X86", [i64], 64,
}
-// GR8_, GR16_, GR32_, GR64_ - Subclasses of GR8, GR16, GR32, and GR64
-// which contain just the "a" "b", "c", and "d" registers. On x86-32,
-// GR16_ and GR32_ are classes for registers that support 8-bit subreg
-// operations. On x86-64, GR16_, GR32_, and GR64_ are classes for registers
-// that support 8-bit h-register operations.
-def GR8_ : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
+// GR8_ABCD, GR16_ABCD, GR32_ABCD, GR64_ABCD - Subclasses of GR8, GR16, GR32,
+// and GR64 which contain just the "a" "b", "c", and "d" registers. On x86-32,
+// GR16_ABCD and GR32_ABCD are classes for registers that support 8-bit subreg
+// operations. On x86-64, GR16_ABCD, GR32_ABCD, and GR64_ABCD are classes for
+// registers that support 8-bit h-register operations.
+def GR8_ABCD : RegisterClass<"X86", [i8], 8, [AL, CL, DL, BL]> {
}
-def GR16_ : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
- let SubRegClassList = [GR8_, GR8_];
+def GR16_ABCD : RegisterClass<"X86", [i16], 16, [AX, CX, DX, BX]> {
+ let SubRegClassList = [GR8_ABCD, GR8_ABCD];
}
-def GR32_ : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
- let SubRegClassList = [GR8_, GR8_, GR16_];
+def GR32_ABCD : RegisterClass<"X86", [i32], 32, [EAX, ECX, EDX, EBX]> {
+ let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD];
}
-def GR64_ : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
- let SubRegClassList = [GR8_, GR8_, GR16_, GR32_];
+def GR64_ABCD : RegisterClass<"X86", [i64], 64, [RAX, RCX, RDX, RBX]> {
+ let SubRegClassList = [GR8_ABCD, GR8_ABCD, GR16_ABCD, GR32_ABCD];
}
// GR8_NOREX, GR16_NOREX, GR32_NOREX, GR64_NOREX - Subclasses of
generated by cgit v1.1 at 2025-03-31 19:17:33 +0000