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| author | Chris Lattner <sabre@nondot.org> | 2008-03-11 19:28:17 +0000 |
|---|---|---|
| committer | Chris Lattner <sabre@nondot.org> | 2008-03-11 19:28:17 +0000 |
| commit | ff19528df3e4ef9820889c7421b4e48b16f82156 (patch) | |
| tree | 7b6d27922240c6e8932cd3fa2e14e120fb80534a /lib/Target/X86 | |
| parent | 267805f2160b05e3982593ad5c644e253754b788 (diff) | |
| download | external_llvm-ff19528df3e4ef9820889c7421b4e48b16f82156.zip external_llvm-ff19528df3e4ef9820889c7421b4e48b16f82156.tar.gz external_llvm-ff19528df3e4ef9820889c7421b4e48b16f82156.tar.bz2 | |
convert a massive if statement to a switch.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@48240 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/X86')
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.cpp | 51 |
1 files changed, 32 insertions, 19 deletions
diff --git a/lib/Target/X86/X86InstrInfo.cpp b/lib/Target/X86/X86InstrInfo.cpp index 20dd263..ba53393 100644 --- a/lib/Target/X86/X86InstrInfo.cpp +++ b/lib/Target/X86/X86InstrInfo.cpp @@ -636,26 +636,39 @@ X86InstrInfo::X86InstrInfo(X86TargetMachine &tm) bool X86InstrInfo::isMoveInstr(const MachineInstr& MI, unsigned& sourceReg, unsigned& destReg) const { - unsigned oc = MI.getOpcode(); - if (oc == X86::MOV8rr || oc == X86::MOV16rr || - oc == X86::MOV32rr || oc == X86::MOV64rr || - oc == X86::MOV16to16_ || oc == X86::MOV32to32_ || - oc == X86::MOV_Fp3232 || oc == X86::MOVSSrr || oc == X86::MOVSDrr || - oc == X86::MOV_Fp3264 || oc == X86::MOV_Fp6432 || oc == X86::MOV_Fp6464 || - oc == X86::FsMOVAPSrr || oc == X86::FsMOVAPDrr || - oc == X86::MOVAPSrr || oc == X86::MOVAPDrr || - oc == X86::MOVSS2PSrr || oc == X86::MOVSD2PDrr || - oc == X86::MOVPS2SSrr || oc == X86::MOVPD2SDrr || - oc == X86::MMX_MOVD64rr || oc == X86::MMX_MOVQ64rr) { - assert(MI.getNumOperands() >= 2 && - MI.getOperand(0).isRegister() && - MI.getOperand(1).isRegister() && - "invalid register-register move instruction"); - sourceReg = MI.getOperand(1).getReg(); - destReg = MI.getOperand(0).getReg(); - return true; + switch (MI.getOpcode()) { + default: + return false; + case X86::MOV8rr: + case X86::MOV16rr: + case X86::MOV32rr: + case X86::MOV64rr: + case X86::MOV16to16_: + case X86::MOV32to32_: + case X86::MOV_Fp3232: + case X86::MOVSSrr: + case X86::MOVSDrr: + case X86::MOV_Fp3264: + case X86::MOV_Fp6432: + case X86::MOV_Fp6464: + case X86::FsMOVAPSrr: + case X86::FsMOVAPDrr: + case X86::MOVAPSrr: + case X86::MOVAPDrr: + case X86::MOVSS2PSrr: + case X86::MOVSD2PDrr: + case X86::MOVPS2SSrr: + case X86::MOVPD2SDrr: + case X86::MMX_MOVD64rr: + case X86::MMX_MOVQ64rr: + assert(MI.getNumOperands() >= 2 && + MI.getOperand(0).isRegister() && + MI.getOperand(1).isRegister() && + "invalid register-register move instruction"); + sourceReg = MI.getOperand(1).getReg(); + destReg = MI.getOperand(0).getReg(); + return true; } - return false; } unsigned X86InstrInfo::isLoadFromStackSlot(MachineInstr *MI, |