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authorRichard Osborne <richard@xmos.com>2013-02-17 22:38:05 +0000
committerRichard Osborne <richard@xmos.com>2013-02-17 22:38:05 +0000
commit8dc741e400213ea8183e09626f0d1f45f14e044f (patch)
treed4c0cc501adc02d7a99e52511d43369ba39e10dc /lib/Target/XCore/Disassembler
parent763c858edeb76173ee4ef5ab9bf7d750db5d8c4f (diff)
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[XCore] Add missing 2r instructions.
These instructions are not targeted by the compiler but it is needed for the MC layer. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175407 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler')
-rw-r--r--lib/Target/XCore/Disassembler/XCoreDisassembler.cpp18
1 files changed, 18 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
index 0bae15c..7e7d396 100644
--- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
+++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp
@@ -100,6 +100,11 @@ static DecodeStatus Decode2RInstruction(MCInst &Inst,
uint64_t Address,
const void *Decoder);
+static DecodeStatus Decode2RImmInstruction(MCInst &Inst,
+ unsigned Insn,
+ uint64_t Address,
+ const void *Decoder);
+
static DecodeStatus DecodeR2RInstruction(MCInst &Inst,
unsigned Insn,
uint64_t Address,
@@ -345,6 +350,19 @@ Decode2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
}
static DecodeStatus
+Decode2RImmInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
+ const void *Decoder) {
+ unsigned Op1, Op2;
+ DecodeStatus S = Decode2OpInstruction(Insn, Op1, Op2);
+ if (S != MCDisassembler::Success)
+ return Decode2OpInstructionFail(Inst, Insn, Address, Decoder);
+
+ Inst.addOperand(MCOperand::CreateImm(Op1));
+ DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder);
+ return S;
+}
+
+static DecodeStatus
DecodeR2RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address,
const void *Decoder) {
unsigned Op1, Op2;