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| author | Richard Osborne <richard@xmos.com> | 2013-01-23 20:08:11 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-23 20:08:11 +0000 |
| commit | 9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b (patch) | |
| tree | 5f3a9a240ddfcaccfa821857f2872af82ffa0f3b /lib/Target/XCore/Disassembler | |
| parent | b09350d9a5639f55c46659b30be12a0c938378ab (diff) | |
| download | external_llvm-9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b.zip external_llvm-9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b.tar.gz external_llvm-9e6a5a37460ff82ad4e3a7aea1c45e2c934ab25b.tar.bz2 | |
Add instruction encodings / disassembly support for l6r instructions.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@173288 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Disassembler')
| -rw-r--r-- | lib/Target/XCore/Disassembler/XCoreDisassembler.cpp | 25 |
1 files changed, 25 insertions, 0 deletions
diff --git a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp index e6861bf..73aeb9c 100644 --- a/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp +++ b/lib/Target/XCore/Disassembler/XCoreDisassembler.cpp @@ -170,6 +170,11 @@ static DecodeStatus DecodeL2RUSBitpInstruction(MCInst &Inst, uint64_t Address, const void *Decoder); +static DecodeStatus DecodeL6RInstruction(MCInst &Inst, + unsigned Insn, + uint64_t Address, + const void *Decoder); + #include "XCoreGenDisassemblerTables.inc" static DecodeStatus DecodeGRRegsRegisterClass(MCInst &Inst, @@ -572,6 +577,26 @@ DecodeL2RUSBitpInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, return S; } +static DecodeStatus +DecodeL6RInstruction(MCInst &Inst, unsigned Insn, uint64_t Address, + const void *Decoder) { + unsigned Op1, Op2, Op3, Op4, Op5, Op6; + DecodeStatus S = + Decode3OpInstruction(fieldFromInstruction(Insn, 0, 16), Op1, Op2, Op3); + if (S != MCDisassembler::Success) + return S; + S = Decode3OpInstruction(fieldFromInstruction(Insn, 16, 16), Op4, Op5, Op6); + if (S != MCDisassembler::Success) + return S; + DecodeGRRegsRegisterClass(Inst, Op1, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op4, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op2, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op3, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op5, Address, Decoder); + DecodeGRRegsRegisterClass(Inst, Op6, Address, Decoder); + return S; +} + MCDisassembler::DecodeStatus XCoreDisassembler::getInstruction(MCInst &instr, uint64_t &Size, |