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| author | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
|---|---|---|
| committer | Evan Cheng <evan.cheng@apple.com> | 2011-06-24 01:44:41 +0000 |
| commit | a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d (patch) | |
| tree | 843b1f6be5ffffef461ce063cf5468368598d40e /lib/Target/XCore/Makefile | |
| parent | 66dddd1da3e036d05f94df82221a97b7d26e3498 (diff) | |
| download | external_llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.zip external_llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.gz external_llvm-a347f85dbeee37a7f2bb68df1a7d4cdfbb7b576d.tar.bz2 | |
Starting to refactor Target to separate out code that's needed to fully describe
target machine from those that are only needed by codegen. The goal is to
sink the essential target description into MC layer so we can start building
MC based tools without needing to link in the entire codegen.
First step is to refactor TargetRegisterInfo. This patch added a base class
MCRegisterInfo which TargetRegisterInfo is derived from. Changed TableGen to
separate register description from the rest of the stuff.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@133782 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/Makefile')
| -rw-r--r-- | lib/Target/XCore/Makefile | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/lib/Target/XCore/Makefile b/lib/Target/XCore/Makefile index 6c1ef88..f67ef51 100644 --- a/lib/Target/XCore/Makefile +++ b/lib/Target/XCore/Makefile @@ -13,7 +13,8 @@ TARGET = XCore # Make sure that tblgen is run, first thing. BUILT_SOURCES = XCoreGenRegisterInfo.h.inc XCoreGenRegisterNames.inc \ - XCoreGenRegisterInfo.inc XCoreGenInstrNames.inc \ + XCoreGenRegisterInfo.inc XCoreGenRegisterDesc.inc \ + XCoreGenInstrNames.inc \ XCoreGenInstrInfo.inc XCoreGenAsmWriter.inc \ XCoreGenDAGISel.inc XCoreGenCallingConv.inc \ XCoreGenSubtarget.inc |