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| author | Richard Osborne <richard@xmos.com> | 2013-01-20 17:18:47 +0000 |
|---|---|---|
| committer | Richard Osborne <richard@xmos.com> | 2013-01-20 17:18:47 +0000 |
| commit | 62b8786d12ceacafd665d4a1fbb6e90af0ec368c (patch) | |
| tree | f9141a727258624ac74e912204bc0119ab9d3f4e /lib/Target/XCore/XCoreInstrFormats.td | |
| parent | 1340833d7c7ed49cf8b19acf53b06a8087ab2bdc (diff) | |
| download | external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.zip external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.tar.gz external_llvm-62b8786d12ceacafd665d4a1fbb6e90af0ec368c.tar.bz2 | |
Add instruction encodings / disassembly support 3r instructions.
It is not possible to distinguish 3r instructions from 2r / rus instructions
using only the fixed bits. Therefore if an instruction doesn't match the
2r / rus format try to decode it as a 3r instruction before returning Fail.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@172984 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrFormats.td')
| -rw-r--r-- | lib/Target/XCore/XCoreInstrFormats.td | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreInstrFormats.td b/lib/Target/XCore/XCoreInstrFormats.td index 44ac45c..b3c2093 100644 --- a/lib/Target/XCore/XCoreInstrFormats.td +++ b/lib/Target/XCore/XCoreInstrFormats.td @@ -33,8 +33,10 @@ class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern> // Instruction formats //===----------------------------------------------------------------------===// -class _F3R<dag outs, dag ins, string asmstr, list<dag> pattern> +class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern> : InstXCore<2, outs, ins, asmstr, pattern> { + let Inst{15-11} = opc; + let DecoderMethod = "Decode3RInstruction"; } class _FL3R<dag outs, dag ins, string asmstr, list<dag> pattern> |