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author | Richard Osborne <richard@xmos.com> | 2013-02-17 22:32:41 +0000 |
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committer | Richard Osborne <richard@xmos.com> | 2013-02-17 22:32:41 +0000 |
commit | 763c858edeb76173ee4ef5ab9bf7d750db5d8c4f (patch) | |
tree | 737b594237e940eeaccbddf6ece0babfff498b2f /lib/Target/XCore/XCoreInstrInfo.td | |
parent | a970dde9060d8994c242bd186bb3636d2caf22d2 (diff) | |
download | external_llvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.zip external_llvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.tar.gz external_llvm-763c858edeb76173ee4ef5ab9bf7d750db5d8c4f.tar.bz2 |
[XCore] Add TSETR instruction.
This instruction is not targeted by the compiler but it is needed for the
MC layer.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175406 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreInstrInfo.td')
-rw-r--r-- | lib/Target/XCore/XCoreInstrInfo.td | 6 |
1 files changed, 5 insertions, 1 deletions
diff --git a/lib/Target/XCore/XCoreInstrInfo.td b/lib/Target/XCore/XCoreInstrInfo.td index 38e2fbc..d366919 100644 --- a/lib/Target/XCore/XCoreInstrInfo.td +++ b/lib/Target/XCore/XCoreInstrInfo.td @@ -395,7 +395,11 @@ def STW_2rus : _F2RUS<0b0000, (outs), defm SHL : F3R_2RBITP<0b00100, 0b10100, "shl", shl>; defm SHR : F3R_2RBITP<0b00101, 0b10101, "shr", srl>; -// TODO tsetr + +// The first operand is treated as an immediate since it refers to a register +// number in another thread. +def TSETR_3r : _F3RImm<0b10111, (outs), (ins i32imm:$a, GRRegs:$b, GRRegs:$c), + "set t[$c]:r$a, $b", []>; // Three operand long def LDAWF_l3r : _FL3R<0b000111100, (outs GRRegs:$dst), |