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authorChris Lattner <sabre@nondot.org>2009-07-28 03:13:23 +0000
committerChris Lattner <sabre@nondot.org>2009-07-28 03:13:23 +0000
commitf0144127b98425d214e59e4a1a4b342b78e3642b (patch)
treecfcb5bc95b5b8060f71ee1b251f0f3e93fbfff2a /lib/Target/XCore/XCoreTargetAsmInfo.cpp
parent7988aff079c54583d7f4d0011ffcfa3d62ff6a85 (diff)
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Rip all of the global variable lowering logic out of TargetAsmInfo. Since
it is highly specific to the object file that will be generated in the end, this introduces a new TargetLoweringObjectFile interface that is implemented for each of ELF/MachO/COFF/Alpha/PIC16 and XCore. Though still is still a brutal and ugly refactoring, this is a major step towards goodness. This patch also: 1. fixes a bunch of dangling pointer problems in the PIC16 backend. 2. disables the TargetLowering copy ctor which PIC16 was accidentally using. 3. gets us closer to xcore having its own crazy target section flags and pic16 not having to shadow sections with its own objects. 4. fixes wierdness where ELF targets would set CStringSection but not CStringSection_. Factor the code better. 5. fixes some bugs in string lowering on ELF targets. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@77294 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'lib/Target/XCore/XCoreTargetAsmInfo.cpp')
-rw-r--r--lib/Target/XCore/XCoreTargetAsmInfo.cpp32
1 files changed, 2 insertions, 30 deletions
diff --git a/lib/Target/XCore/XCoreTargetAsmInfo.cpp b/lib/Target/XCore/XCoreTargetAsmInfo.cpp
index fee0a22..fd8c9d7 100644
--- a/lib/Target/XCore/XCoreTargetAsmInfo.cpp
+++ b/lib/Target/XCore/XCoreTargetAsmInfo.cpp
@@ -1,4 +1,4 @@
-//===-- XCoreTargetAsmInfo.cpp - XCore asm properties -----------*- C++ -*-===//
+//===-- XCoreTargetAsmInfo.cpp - XCore asm properties ---------------------===//
//
// The LLVM Compiler Infrastructure
//
@@ -6,41 +6,13 @@
// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
-//
-// This file contains the declarations of the XCoreTargetAsmInfo properties.
-// We use the small section flag for the CP relative and DP relative
-// flags. If a section is small and writable then it is DP relative. If a
-// section is small and not writable then it is CP relative.
-//
-//===----------------------------------------------------------------------===//
#include "XCoreTargetAsmInfo.h"
-#include "XCoreTargetMachine.h"
-#include "llvm/GlobalVariable.h"
-#include "llvm/ADT/StringExtras.h"
-
using namespace llvm;
-XCoreTargetAsmInfo::XCoreTargetAsmInfo(const XCoreTargetMachine &TM)
+XCoreTargetAsmInfo::XCoreTargetAsmInfo(const TargetMachine &TM)
: ELFTargetAsmInfo(TM) {
SupportsDebugInformation = true;
- TextSection = getOrCreateSection("\t.text", true, SectionKind::Text);
- DataSection = getOrCreateSection("\t.dp.data", false, SectionKind::DataRel);
- BSSSection_ = getOrCreateSection("\t.dp.bss", false, SectionKind::BSS);
-
- // TLS globals are lowered in the backend to arrays indexed by the current
- // thread id. After lowering they require no special handling by the linker
- // and can be placed in the standard data / bss sections.
- TLSDataSection = DataSection;
- TLSBSSSection = BSSSection_;
-
- if (TM.getSubtargetImpl()->isXS1A())
- // FIXME: Why is this writable???
- ReadOnlySection = getOrCreateSection("\t.dp.rodata", false,
- SectionKind::DataRel);
- else
- ReadOnlySection = getOrCreateSection("\t.cp.rodata", false,
- SectionKind::ReadOnly);
Data16bitsDirective = "\t.short\t";
Data32bitsDirective = "\t.long\t";
Data64bitsDirective = 0;